Abstract: A method of making a three-dimensional fiber preform for fabricating an annular part out of carbon-carbon composite material, the method including stacking layers of a fiber sheet made up of carbon yarns or tows, needling the layers one by one as they are superposed so as to bond them together, and locally modifying the electromagnetic properties of the fiber preform by increasing the fiber density of the layers of the fiber sheet that are situated at half-thickness of the fiber preform.

Abstract: A one-piece or otherwise unitary annular shim member made from a perforated metallic material is used to maintain a space between stacked annular preforms during a manufacturing process, such as densification. The metallic material used preferably can withstand at least the temperatures encountered during densification. The one-piece structure advantageously simplifies the arrangement of the preforms in a process chamber and causes less deformation in the preforms. In one example, the shim member is made from a metallic mesh and may utilize a crimped weave structure.

Abstract: A method of making a three-dimensional fiber preform for fabricating an annular part out of carbon-carbon composite material, the method including stacking layers of a fiber sheet made up of carbon yarns or tows, needling the layers one by one as they are superposed so as to bond them together, and locally modifying the electromagnetic properties of the fiber preform by increasing the fiber density of the layers of the fiber sheet that are situated at half-thickness of the fiber preform.

Abstract: The present invention describes a method of CVI densification in which particular arrangements and mixtures of undensified porous substrates and partially densified porous substrates are arranged in particular ways in order to use the thermal characteristics of the partially densified porous substrates to better distribute heat throughout a CVI furnace and thereby improve densification.

Abstract: A method of densifying porous substrates, such as brake performs, using a liquid precursor, in which the rate at which “fresh” or “new” liquid precursor is consumed is reduced by maintaining the liquid precursor being used for the densification at a purity level that is less that pure but still chemically suitable for obtaining the desired densification product.

Abstract: The present invention relates to an inductive heating apparatus, particularly using a liquid deposition precursor, for densifying porous articles. The inductive heating apparatus using induction coils that are made from machined or milled flat metal plates, such as copper plate, instead of bending a member (especially a hollow member) into a coil shape. The induction coils according to the present invention can be more precisely and more consistently fabricated than conventional bending techniques.

Abstract: A method of controlling power applied to an induction coil assembly used for densifying porous articles with a liquid matrix precursor. The control of applied power addresses dynamic changes in the electrical characteristics of the porous article being densified as it becomes denser. In particular, the power applied is controlled in accordance with changes in resonant frequency of the coupled system of the induction heating system and the porous article.

Abstract: The present invention describes a method of CVI densification in which particular arrangements and mixtures of undensified porous substrates and partially densified porous substrates are arranged in particular ways in order to use the thermal characteristics of the partially densified porous substrates to better distribute heat throughout a CVI furnace and thereby improve densification.

Abstract: A circuit carrier and a package structure thereof are provided. The circuit carrier comprises a substrate having a surface, a plurality of passive component electrode pads or a plurality of passive component electrode planes on the surface of the substrate for electrically connecting a passive component corresponding to the plurality of passive component electrode pads, and a solder mask layer covering the surface of the substrate and including at least a solder mask opening, that entirely exposing the passive component electrode pads or a portion of the surface of each the passive component electrode plane corresponding to the passive component. Because there is no solder mask layer between the bottom of the passive component and the substrate, the gap between the passive component and the substrate will become wider. Hence, remaining flux can be entirely removed in order to increase the yield rate of the subsequent high temperature process.

Abstract: A one-piece or otherwise unitary annular shim member made from a carbon material is used to maintain a space between stacked annular preforms during a manufacturing process, such as densification. The one-piece structure advantageously simplifies the arrangement of the preforms in a process chamber and causes less deformation in the preforms. The carbon composition also provides beneficial thermal effects that improve the densification process. A debonding coating is provided on the annular shim member in order to facilitate separation of the annular preforms from the shim members.

Abstract: A one-piece or otherwise unitary annular shim member made from a perforated metallic material is used to maintain a space between stacked annular preforms during a manufacturing process, such as densification. The metallic material used preferably can withstand at least the temperatures encountered during densification. The one-piece structure advantageously simplifies the arrangement of the preforms in a process chamber and causes less deformation in the preforms. In one example, the shim member is made from a metallic mesh and may utilize a crimped weave structure.

Abstract: The present invention provides a chip package structure, comprising: a glass substrate having a substrate surface; a circuit layer on the substrate surface, wherein the circuit layer comprises an interconnection structure; at least a die on the circuit layer, wherein the die is coupled to the interconnection structure; and a plurality of contacts on the circuit layer, wherein the contacts are coupled to the interconnection structure.

Abstract: A hybrid integrated circuit (IC) package substrate at least comprising a plurality of patterned conductive layers stacked over each other. The outermost patterned conductive layer has a plurality of bonding pads thereon. The hybrid IC package substrate also has a plurality of dielectric layers respectively sandwiched between two neighboring patterned conductive layers. At least one of the dielectric layers is a ceramic dielectric layer and at least one of the remaining dielectric layers is an organic dielectric layer. There is also a plurality of vias passing through at least one of the dielectric layers for connecting at least two patterned conductive layers electrically.

Abstract: A circuit carrier and a package structure thereof are provided. The circuit carrier comprises a substrate having a surface, a plurality of passive component electrode pads or a plurality of passive component electrode planes on the surface of the substrate for electrically connecting a passive component corresponding to the plurality of passive component electrode pads, and a solder mask layer covering the surface of the substrate and including at least a solder mask opening, that entirely exposing the passive component electrode pads or a portion of the surface of each the passive component electrode plane corresponding to the passive component. Because there is no solder mask layer between the bottom of the passive component and the substrate, the gap between the passive component and the substrate will become wider. Hence, remaining flux can be entirely removed in order to increase the yield rate of the subsequent high temperature process.

Abstract: A conductive wiring layer structure, applied to the conductive wiring layer structure under bonding pads of a die. The die has a substrate and can be partitioned into a central core circuit and a peripheral bonding pad area. The conductive wire layer structure has a plurality of trapezium conductive wiring regions and a plurality of inverse trapezium conductive wiring regions alternately arranged in the bonding pad area. Each of the equilateral and inverse trapezium conductive wiring regions has a plurality of dielectric layers and a plurality of conductive wiring layers alternately overlaying each other on the substrate. The conductive wiring layers of the trapezium conductive wiring region are wider as approaching the substrate, and become narrower as distant away from the substrate. The conductive wiring layers of the inverse trapezium conductive wiring region are narrower as approaching the substrate, and wider as distant away from the substrate.

Abstract: A manufacturing process of package substrate is disclosed. The process is firstly disposing at least one passive component between a power pad and a ground pad of a package substrate, wherein two electrodes of the passive component connecting to the power pad and the ground pad, respectively; and then forming a metal layer on the electrodes of the passive component and exposed surfaces of all the conductive pads of the substrate. Therefore, during the subsequent wire bonding process, the two ends of the conductive wire can be respectively connected to a die pad of a die and an electrode of the passive component for improving yield and reliability of chip package fabrication.

Abstract: A chip package structure is provided. The chip package at least comprises a carrier, a die, a passive component, a plurality of first conducting wires, a second conducting wire, and a dielectric material. Two electrodes of the passive component are electrically connected to the power pad and the ground pad, respectively. Since one end of the conducting wire is directly connected to one electrode of the passive component, the length of the conducting wire can be effectively shortened. Hence the signal transmission path is shorter and there is more layout space for conducting wires.

Abstract: A chip package structure comprising a carrier, a chip, a plurality of passive components, a plurality of conductive wires and some insulating material is provided. The passive components are attached to the surface of the carrier with its electrodes connected to a power contact and a ground contact respectively. The conductive wires cross over the passive components with its ends connected respectively to a bonding pad on the chip and a signal contact close to the edge of the carrier. With the wires crossing over the passive components that are positioned close to a chip bonding area of the carrier, contact between the wires and the electrodes is prevented and the space for accommodating conductive wires is increased.

Abstract: A hybrid integrated circuit (IC) package substrate at least comprising a plurality of patterned conductive layers stacked over each other. The outermost patterned conductive layer has a plurality of bonding pads thereon. The hybrid IC package substrate also has a plurality of dielectric layers respectively sandwiched between two neighboring patterned conductive layers. At least one of the dielectric layers is a ceramic dielectric layer and at least one of the remaining dielectric layers is an organic dielectric layer. There is also a plurality of vias passing through at least one of the dielectric layers for connecting at least two patterned conductive layers electrically.

Abstract: The present invention provides a chip package structure, comprising: a glass substrate having a substrate surface; a circuit layer on the substrate surface, wherein the circuit layer comprises an interconnection structure; at least a die on the circuit layer, wherein the die is coupled to the interconnection structure; and a plurality of contacts on the circuit layer, wherein the contacts are coupled to the interconnection structure.