Abstract: A bump arrangement of a flip-chip is disclosed. The bump arrangement comprises: a conductive bumps array formed at a core region of the flip-chip, a first ring of conductive bumps surrounding the conductive bumps array, a second ring surrounding the first ring, a third ring surrounding the second ring, and a fourth ring surrounding the third ring. In the four rings of bumps, the bumps of the third ring and the fourth ring are staggered each other and most of them are provided for I/O signal terminal so as to reduce the length conductive traces for I/O signal connection. The bumps in the first and the second ring are provided for power connection or ground connection. The first ring, the second ring, the third ring, the fourth ring and the bump at the core region are connected to conductive traces of an interconnection layer through a redistribution layer. The redistribution layer is located in between a passivation layer and the interconnection layer.

Abstract: A bump arrangement of a flip-chip is disclosed. The bump arrangement comprises: a conductive bumps array formed at a core region of the flip-chip, a first ring of conductive bumps surrounding the conductive bumps array, a second ring surrounding the first ring, a third ring surrounding the second ring, and a fourth ring surrounding the third ring. In the four rings of bumps, the bumps of the third ring and the fourth ring are staggered each other and most of them are provided for I/O signal terminal so as to reduce the length conductive traces for I/O signal connection. The bumps in the first and the second ring are provided for power connection or ground connection. The first ring, the second ring, the third ring, the fourth ring and the bump at the core region are connected to conductive traces of an interconnection layer through a redistribution layer. The redistribution layer is located in between a passivation layer and the interconnection layer.

Abstract: A conductive wiring layer structure, applied to the conductive wiring layer structure under bonding pads of a die. The die has a substrate and can be partitioned into a central core circuit and a peripheral bonding pad area. The conductive wire layer structure has a plurality of trapezium conductive wiring regions and a plurality of inverse trapezium conductive wiring regions alternately arranged in the bonding pad area. Each of the equilateral and inverse trapezium conductive wiring regions has a plurality of dielectric layers and a plurality of conductive wiring layers alternately overlaying each other on the substrate. The conductive wiring layers of the trapezium conductive wiring region are wider as approaching the substrate, and become narrower as distant away from the substrate. The conductive wiring layers of the inverse trapezium conductive wiring region are narrower as approaching the substrate, and wider as distant away from the substrate.