Patents by Inventor Kenshi Tada

Kenshi Tada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120119322
    Abstract: A plurality of light-shielding films etc. are formed on a surface of a first insulating film. Then, a dummy pattern is formed on a surface of a second insulating film between adjoining ones of the light-shielding films etc., so that a height of the dummy pattern is equal to that of the second insulating film on the light-shielding films etc., as measured from the surface of the first insulating film. Thereafter, a third insulating film covering the dummy pattern and having a flat surface is formed over the surface of the second insulating film. Subsequently, a base layer is bonded to a support substrate so that the flat surface of the third insulating film faces the support substrate. A semiconductor device is manufactured in this manner.
    Type: Application
    Filed: June 8, 2010
    Publication date: May 17, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Kenshi Tada
  • Publication number: 20120038022
    Abstract: Disclosed is a glass substrate (20) that is capable of constituting a semiconductor device (10) when a monocrystalline silicon thin film (90) is provided on the surface of the substrate by transfer. The surface of the glass substrate (20) has a receiving surface (22) onto which the monocrystalline silicon thin film (90) can be provided. The height of the ripples on the receiving surface (22) having a period of 200 to 500 microns is no more than 0.40 nm.
    Type: Application
    Filed: October 26, 2009
    Publication date: February 16, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Kazuhide Tomiyasu, Yutaka Takafuji, Yasumori Fukushima, Kazuo Nakagawa, Kenshi Tada, Michiko Takei, Shin Matsumoto
  • Publication number: 20110309467
    Abstract: Disclosed is a semiconductor device including a substrate for bonding (10a), and a semiconductor element part (25aa) which is bonded to the substrate (10a), and in which an element pattern (T) is formed, wherein in a bonded interface between the substrate (10a) and the semiconductor element part (25aa), recessed portions (23a) are formed in at least one of the substrate (10a) and the semiconductor element part (25aa).
    Type: Application
    Filed: November 25, 2009
    Publication date: December 22, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Shin Matsumoto, Yutaka Takafuji, Yasumori Fukushima, Kazuhide Tomiyasu, Kenshi Tada
  • Publication number: 20110284860
    Abstract: A method for producing a semiconductor device includes a step of forming a first insulation film, a step of forming a separation layer in a base layer, a step of forming a light-blocking film on the surface of the first insulation film, a step of forming a second insulation film such that the light-blocking film is covered, a step of affixing the base layer provided with the light-blocking film to a substrate, a step of separating and removing along the separation layer a portion of the base layer affixed to the substrate, and a step of forming a semiconductor layer such that at least a portion thereof overlaps with the light-blocking film.
    Type: Application
    Filed: December 4, 2009
    Publication date: November 24, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Kenshi Tada
  • Publication number: 20110042693
    Abstract: A semiconductor device (10) includes a support substrate (14), an adhered device part (11) adhered to the support substrate (14), a multilayer device part (13) stacked on the adhered device part (11), and an adjacent device part (12) formed in a region adjacent to the adhered device part on the support substrate (14). The adhered device part (11), the multilayer device part (13), and the adjacent device part (12) are electrically connected to one another.
    Type: Application
    Filed: April 9, 2009
    Publication date: February 24, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Kenshi Tada, Yutaka Takafuji, Yasumori Fukushima, Kazuhide Tomiyasu, Michiko Takei, Kazuo Nakagawa, Shin Matsumoto
  • Publication number: 20110006376
    Abstract: The present invention provides a semiconductor device capable of improving subthreshold characteristics of a PMOS transistor that is included in a thinned base layer and bonded to another substrate, a production method of such a semiconductor device, and a display device. The semiconductor device of the present invention is a semiconductor device, including: a substrate; and a device part bonded to the substrate, the device part including a base layer and a PMOS transistor, the PMOS transistor including a first electrical conduction path and a first gate electrode, the first electrical conduction path being provided inside the base layer on a side where the first gate electrode is disposed.
    Type: Application
    Filed: March 3, 2009
    Publication date: January 13, 2011
    Inventors: Yasumori Fukushima, Yutaka Takafuji, Masao Moriguchi, Kenshi Tada, Steven Roy Droes
  • Publication number: 20100295105
    Abstract: A method for manufacturing a semiconductor device includes: an element portion formation step of forming an element portion on a base layer; a delaminating layer formation step of forming a delaminating layer in the base layer; a bonding step of bonding the base layer having the element portion to a substrate; and a separation step of separating and removing a portion of the base layer in the depth direction along the delaminating layer by heating the base layer bonded to the substrate. The method further includes, after the separation step, an ion implantation step of ion-implanting a p-type impurity element in the base layer for adjusting the impurity concentration of a p-type region of the element.
    Type: Application
    Filed: September 25, 2008
    Publication date: November 25, 2010
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yasumori Fukushima, Kazuhide Tomiyasu, Yutaka Takafuji, Kenshi Tada, Michiko Takei
  • Publication number: 20100289037
    Abstract: The present invention provides a semiconductor device having a plurality of MOS transistors with controllable threshold values in the same face and easy to manufacture, a manufacturing method thereof and a display device. The invention is a semiconductor device having a plurality of MOS transistors in the same face each having a structure formed by stacking a semiconductor active layer, a gate insulator, and a gate electrode, wherein the semiconductor device includes: an insulating layer stacked on a side opposite to a gate electrode side of the semiconductor active layer; and a conductive electrode stacked on a side opposite to a semiconductor active layer side of the insulating layer and extending over at least two of the plurality of MOS transistors.
    Type: Application
    Filed: October 10, 2008
    Publication date: November 18, 2010
    Inventors: Shin Matsumoto, Yutaka Takafuji, Yasumori Fukushima, kenshi Tada
  • Publication number: 20100283104
    Abstract: An element portion forming step includes an insulating film forming step of forming an insulating film on a surface of a base layer, a conductive layer forming step of uniformly forming a conductive layer on a surface of the insulating film, and an electrode forming step of patterning the conductive layer to form an electrode. A delamination layer forming step of ion implanting a delamination material into the base layer to form a delamination layer is performed before the electrode forming step.
    Type: Application
    Filed: November 25, 2008
    Publication date: November 11, 2010
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Kenshi Tada, Yutaka Takafuji, Yasumori Fukushima, Kazuhide Tomiyasu, Michiko Takei, Kazuo Nakagawa, Shin Matsumoto
  • Publication number: 20100270658
    Abstract: A method is disclosed for producing a semiconductor device produced by (i) doping hydrogen ions or rare gas ions into a device substrate in which a transfer layer (16) is formed, (ii) then bonding the device substrate to a carrier target substrate, and (iii) transferring the transfer layer (16) onto the carrier substrate (30) by cleaving the device substrate along a portion in which the hydrogen ions or the rare gas ions are doped, the method including providing a blocking layer (11) for blocking diffusion of a bubble-causing substance between (i) a bonding surface (13), which serves as a bonding interface between the device substrate and the carrier substrate, and (ii) the transfer layer (16). This prevents bubbles from forming at the bonding interface between the semiconductor substrate and the target substrate due to the diffusion of the bubble-causing substance.
    Type: Application
    Filed: September 12, 2008
    Publication date: October 28, 2010
    Inventors: Kazuo Nakagawa, Michiko Takei, Yasumori Fukushima, Kazuhide Tomiyasu, Shin Matsumoto, Kenshi Tada, Yutaka Takafuji
  • Publication number: 20100252885
    Abstract: A semiconductor device (10) is formed by bonding a semiconductor substrate (1) including a CMOS transistor (3) to a glass substrate (2). The semiconductor substrate (1) is formed by partial separation at a separation layer. A P-type high concentration impurity region (39n) is formed in electric connection with a channel region (35n) of an NMOS transistor (3n) so that an electric potential of the channel region (35n) is fixed. The P-type high concentration impurity region (39n) has the same P conductive type as that of the channel region (35n) and also has a concentration higher than that of the channel region (35n). An N-type high concentration impurity region (39p) is formed in electric connection with a channel region (35p) of a PMOS transistor (3p) so that an electric potential of the channel region (35p) is fixed. The N-type high concentration impurity region (39p) has the same N conductive type as that of the channel region (35p) and also has a concentration higher than that of the channel region (35p).
    Type: Application
    Filed: September 19, 2008
    Publication date: October 7, 2010
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yasumori Fukushima, Yutaka Takafuji, Kenshi Tada
  • Publication number: 20100244185
    Abstract: The present invention provides a semiconductor device, a single-crystal semiconductor thin film-including substrate, and production methods thereof, each allowing single-crystal semiconductor thin film-including single-crystal semiconductor elements produced by being transferred onto a low heat resistant insulating substrate to have enhanced transistor characteristics. The present invention is a production method of a semiconductor device including single-crystal semiconductor thin film-including single-crystal semiconductor elements on an insulating substrate, the production method including the successive steps of a first heat treatment step and a second heat treatment step, wherein in the first heat treatment step, a single-crystal semiconductor thin film undergoes a heat treatment at lower than 650° C.
    Type: Application
    Filed: October 22, 2008
    Publication date: September 30, 2010
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yutaka Takafuji, Yasumori Fukushima, Kenshi Tada, Kazuo Nakagawa, Shin Matsumoto, Kazuhide Tomiyasu
  • Patent number: 7711526
    Abstract: A transistor model for a simulator simulates a resistance between a source region and a drain region with a model equation which has terms representing resistance values corresponding respectively to areas of mutually different impurity concentrations below a gate section in simulating characteristics of a transistor. At least two of the terms each having a threshold parameter indicating a voltage at which a semiconductor element composed of the associated region and regions adjacent to that region changes from an ON state to an OFF state. The threshold parameters of the terms being specified independently from each other. Thus, the characteristics of a transistor having a set of areas of mutually different impurity concentrations below a gate section, inclusive of subthreshold regions which are difficult to evaluate through actual measurement, can be simulated to high accuracy while preserving a good fit with a capacitance model.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: May 4, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuhiro Maeda, Tamotsu Sakai, Yasushi Kubota, Shigeki Imai, Kenshi Tada, Kenji Taniguchi
  • Publication number: 20050015235
    Abstract: A transistor model for a simulator simulates a resistance between a source region and a drain region with a model equation which has terms representing resistance values corresponding respectively to areas of mutually different impurity concentrations below a gate section in simulating characteristics of a transistor. At least two of the terms each having a threshold parameter indicating a voltage at which a semiconductor element composed of the associated region and regions adjacent to that region changes from an ON state to an OFF state. The threshold parameters of the terms being specified independently from each other. Thus, the characteristics of a transistor having a set of areas of mutually different impurity concentrations below a gate section, inclusive of subthreshold regions which are difficult to evaluate through actual measurement, can be simulated to high accuracy while preserving a good fit with a capacitance model.
    Type: Application
    Filed: July 15, 2004
    Publication date: January 20, 2005
    Applicants: Sharp Kabushiki Kaisha, Kenji Taniguchi
    Inventors: Kazuhiro Maeda, Tamotsu Sakai, Yasushi Kubota, Shigeki Imai, Kenshi Tada, Kenji Taniguchi