Patents by Inventor Kensuke Ishikawa
Kensuke Ishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11935784Abstract: A vertical layer stack including a bit-line-level dielectric layer and an etch stop dielectric layer can be formed over an array region. Bit-line trenches are formed through the vertical layer stack. Bit-line-trench fill structures are formed in the bit-line trenches. Each of the bit-line-trench fill structures includes a stack of a bit line and a capping dielectric strip. At least one via-level dielectric layer can be formed over the vertical layer stack. A bit-line-contact via cavity can be formed through the at least one via-level dielectric layer and one of the capping dielectric strips. A bit-line-contact via structure formed in the bit-line-contact via cavity includes a stepped bottom surface including a top surface of one of the bit lines, a sidewall segment of the etch stop dielectric layer, and a segment of a top surface of the etch stop dielectric layer.Type: GrantFiled: June 11, 2021Date of Patent: March 19, 2024Assignee: SANDISK TECHNOLOGIES LLCInventors: Fumitaka Amano, Yusuke Osawa, Kensuke Ishikawa, Mitsuteru Mushiga, Motoki Kawasaki, Shinsuke Yada, Masato Miyamoto, Syo Fukata, Takashi Kashimura, Shigehiro Fujino
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Publication number: 20230361061Abstract: Bonding strength and yield can be enhanced by providing a mating pair of a convex bonding surface and a concave bonding surface. The convex bonding surface can be provided by employing a conductive barrier layer having a higher electrochemical potential than copper. The concave bonding surface can be provided by employing a conductive barrier layer having a lower electrochemical potential than copper. Alternatively additionally, a copper material portion in a bonding pad may include at least 10% volume fraction of (200) copper grains to provide high volume expansion toward a mating copper material portion. The mating copper material portion may be formed with at least 95% volume fraction of (111) copper grains to provide high surface diffusivity, or may be formed with at least 10% volume fraction of (200) copper grains to provide high volume expansion.Type: ApplicationFiled: May 9, 2022Publication date: November 9, 2023Inventors: Shingo TOTANI, Fumitaka AMANO, Kensuke ISHIKAWA
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Publication number: 20230361069Abstract: A bonded assembly includes a first semiconductor die containing first semiconductor devices and a first bonding pad embedded within a first silicon oxide layer, where the first bonding pad includes a first copper containing portion, a second semiconductor die containing second semiconductor devices and a second bonding pad that is embedded within a second silicon oxide layer and is bonded to the first bonding pad via metal-to-metal bonding, where the second bonding pad includes a second copper containing portion, and at least one metal silicon oxide layer interposed between the first bonding pad and the second silicon oxide layer. In one embodiment, the at least one metal silicon oxide layer is a manganese silicon oxide layer.Type: ApplicationFiled: September 9, 2022Publication date: November 9, 2023Inventors: Kensuke ISHIKAWA, Fumitaka AMANO, Shingo TOTANI, Linghan CHEN
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Publication number: 20230127904Abstract: A method of forming a semiconductor structure includes forming a semiconductor device over a substrate, forming a combination of a connection-level dielectric layer and a connection-level metal interconnect structure over the semiconductor device, where the connection-level metal interconnect structure is electrically connected to a node of the semiconductor device and is embedded in the connection-level dielectric layer, forming a line-and-via-level dielectric layer over the connection-level dielectric layer, forming an integrated line-and-via cavity through the line-and-via-level dielectric layer over the connection-level metal interconnect structure, selectively growing a conductive via structure containing cobalt from a bottom of the via portion of the integrated line-and-via cavity without completely filling a line portion of the integrated line-and-via cavity, and forming a copper-based conductive line structure that contains copper at an atomic percentage that is greater than 90% in the line portion ofType: ApplicationFiled: August 23, 2022Publication date: April 27, 2023Inventors: Shingo TOTANI, Kensuke ISHIKAWA, Fumitaka AMANO
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Publication number: 20230128326Abstract: A method includes forming a semiconductor device, forming a combination of a connection-level dielectric layer and a connection-level metal interconnect structure over the semiconductor device, forming a line-and-via-level dielectric layer over the connection-level dielectric layer, forming an integrated line-and-via cavity through the line-and-via-level dielectric layer over the connection-level metal interconnect structure, selectively growing a conductive via structure consisting essentially of an elemental metal that is not copper from a physically exposed conductive surface located at a bottom of the via portion of the integrated line-and-via cavity without filling a line portion of the integrated line-and-via cavity, and forming a copper-based conductive line structure that includes copper at an atomic percentage that is greater than 90% in the line portion of the integrated line-and-via cavity.Type: ApplicationFiled: October 25, 2021Publication date: April 27, 2023Inventors: Fumitaka AMANO, Kensuke ISHIKAWA
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Publication number: 20220399232Abstract: A vertical layer stack including a bit-line-level dielectric layer and an etch stop dielectric layer can be formed over an array region. Bit-line trenches are formed through the vertical layer stack. Bit-line-trench fill structures are formed in the bit-line trenches. Each of the bit-line-trench fill structures includes a stack of a bit line and a capping dielectric strip. At least one via-level dielectric layer can be formed over the vertical layer stack. A bit-line-contact via cavity can be formed through the at least one via-level dielectric layer and one of the capping dielectric strips. A bit-line-contact via structure formed in the bit-line-contact via cavity includes a stepped bottom surface including a top surface of one of the bit lines, a sidewall segment of the etch stop dielectric layer, and a segment of a top surface of the etch stop dielectric layer.Type: ApplicationFiled: June 11, 2021Publication date: December 15, 2022Inventors: Fumitaka AMANO, Yusuke OSAWA, Kensuke ISHIKAWA, Mitsuteru MUSHIGA, Motoki KAWASAKI, Shinsuke YADA, Masato MIYAMOTO, Syo FUKATA, Takashi KASHIMURA, Shigehiro FUJINO
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Publication number: 20220336394Abstract: A bonded assembly includes a first semiconductor die that includes first metallic bonding structures embedded within a first bonding-level dielectric layer, and a second semiconductor die that includes second metallic bonding structures embedded within a second bonding-level dielectric layer and bonded to the first metallic bonding structures by metal-to-metal bonding. One of the first metallic bonding structures a pad portion, and a via portion located between the pad portion and the first semiconductor device, the via portion having second tapered sidewalls.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Inventors: Kensuke ISHIKAWA, Shingo TOTANI, Fumitaka AMANO, Rahul SHARANGPANI
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Publication number: 20190244855Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.Type: ApplicationFiled: April 16, 2019Publication date: August 8, 2019Inventors: Junji NOGUCHI, Takayuki OSHIMA, Noriko MIURA, Kensuke ISHIKAWA, Tomio IWASAKI, Kiyomi KATSUYAMA, Tatsuyuki SAITO, Tsuyoshi TAMARU, Hizuru YAMAGUCHI
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Patent number: 10304726Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.Type: GrantFiled: September 21, 2018Date of Patent: May 28, 2019Assignee: Renesas Electronics CorporationInventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
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Publication number: 20190035678Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.Type: ApplicationFiled: September 21, 2018Publication date: January 31, 2019Inventors: Junji NOGUCHI, Takayuki OSHIMA, Noriko MIURA, Kensuke ISHIKAWA, Tomio IWASAKI, Kiyomi KATSUYAMA, Tatsuyuki SAITO, Tsuyoshi TAMARU, Hizuru YAMAGUCHI
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Patent number: 10121693Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.Type: GrantFiled: October 9, 2017Date of Patent: November 6, 2018Assignee: Renesas Electronics CorporationInventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
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Patent number: 10115735Abstract: A semiconductor device includes a silicon surface, a titanium silicide layer contacting the silicon surface, a first titanium nitride layer located over the titanium silicide layer, a titanium oxynitride layer contacting the first titanium nitride layer, a second titanium nitride layer contacting the titanium oxynitride layer, and a metal fill layer located over the second titanium nitride layer.Type: GrantFiled: June 8, 2017Date of Patent: October 30, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Fumitaka Amano, Kensuke Ishikawa, Shinya Inoue, Michiaki Sano
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Publication number: 20180247954Abstract: A semiconductor device includes a silicon surface, a titanium silicide layer contacting the silicon surface, a first titanium nitride layer located over the titanium silicide layer, a titanium oxynitride layer contacting the first titanium nitride layer, a second titanium nitride layer contacting the titanium oxynitride layer, and a metal fill layer located over the second titanium nitride layer.Type: ApplicationFiled: June 8, 2017Publication date: August 30, 2018Inventors: Fumitaka Amano, Kensuke Ishikawa, Shinya Inoue, Michiaki Sano
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Publication number: 20180047620Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.Type: ApplicationFiled: October 9, 2017Publication date: February 15, 2018Inventors: Junji NOGUCHI, Takayuki OSHIMA, Noriko MIURA, Kensuke ISHIKAWA, Tomio IWASAKI, Kiyomi KATSUYAMA, Tatsuyuki SAITO, Tsuyoshi TAMARU, Hizuru YAMAGUCHI
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Patent number: 9818639Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.Type: GrantFiled: March 27, 2017Date of Patent: November 14, 2017Assignee: Renesas Electronics CorporationInventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
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Patent number: 9779312Abstract: Provided is a system capable of further reducing risk such as a contact between a moving body such as a vehicle and a traffic participant present around the moving body. According to an environment recognition system (1) of the present invention, a database (10) stores each of a plurality of reference symbol strings describing the state of an environmental element constituting each of a plurality of scenes assumed to be around the moving body. A first arithmetic processing element (11) detects a scene around the moving body and generates a symbol string describing the state of the environmental element constituting the detected scene. A second arithmetic processing element (12) evaluates similarity between the symbol string and each of the plurality of reference symbol strings stored in the database (10).Type: GrantFiled: January 27, 2016Date of Patent: October 3, 2017Assignee: HONDA MOTOR CO., LTD.Inventors: Yoshiaki Sakagami, Taku Osada, Kensuke Ishikawa
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Publication number: 20170200637Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.Type: ApplicationFiled: March 27, 2017Publication date: July 13, 2017Inventors: Junji NOGUCHI, Takayuki OSHIMA, Noriko MIURA, Kensuke ISHIKAWA, Tomio IWASAKI, Kiyomi KATSUYAMA, Tatsuyuki SAITO, Tsuyoshi TAMARU, Hizuru YAMAGUCHI
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Patent number: 9659867Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.Type: GrantFiled: September 22, 2016Date of Patent: May 23, 2017Assignee: Renesas Electronics CorporationInventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
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Publication number: 20170011994Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.Type: ApplicationFiled: September 22, 2016Publication date: January 12, 2017Inventors: Junji NOGUCHI, Takayuki OSHIMA, Noriko MIURA, Kensuke ISHIKAWA, Tomio IWASAKI, Kiyomi KATSUYAMA, Tatsuyuki SAITO, Tsuyoshi TAMARU, Hizuru YAMAGUCHI
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Patent number: 9490213Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.Type: GrantFiled: May 1, 2015Date of Patent: November 8, 2016Assignee: Renesas Electronics CorporationInventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi