Abstract: A media processing method for performing media processing by causing a processor to execute plural program modules, includes controlling input/output of media data, determining at least one call time, and calling a second program module in a second layer at each determined call time, by executing a first program module in a first layer, the first layer being higher than the second layer. The method further includes causing the processor to perform data conversion on the media data, by executing the second program module in the second layer, the data conversion being part of the media processing.

Abstract: A media processing method for performing media processing by causing a processor to execute plural program modules, includes controlling input/output of media data, determining at least one call time, and calling a second program module in a second layer at each determined call time, by executing a first program module in a first layer, the first layer being higher than the second layer. The method further includes causing the processor to perform data conversion on the media data, by executing the second program module in the second layer, the data conversion being part of the media processing.

Abstract: A media processing method for performing media processing by causing a processor to execute plural program modules, including: a first step of controlling input/output of media data, determining at least one call time, and calling a second program module in a second layer at each determined call time, by executing a first program module in a first layer, the first layer being higher than the second layer; a second step of calling at least one third program module in a third layer, the third layer being lower than the second layer, by executing the second program module in the second layer; and a third step of causing the processor to perform data conversion on the media data, the data conversion being an element of the media processing, by executing the third program module in the third layer.

Abstract: When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract: According to program converting step S100 of the present invention, classes whose objects are created out of the classes included in a program are detected and the result is recorded in an analysis information storing section 12 at an object analyzing step S104, functions (unnecessary functions) regarding classes whose objects are not created are analyzed in accordance with information held in the analysis information storing section 12 and the result is recorded in the analysis information storing section 12 at an unnecessary function analyzing step S105, and definitions of the unnecessary functions are deleted in accordance with information held in the analysis information storing section 12 at an unnecessary function deleting step S106.

Abstract: A display control selection section receives a plurality of display control requirements for screen display and selects and outputs to an input timing control section a display control requirement capable of being processed within a single screen non-display interval out of the received display control requirements. The input timing control section outputs the display control requirement selected by the display control selection section to a display processor when the screen non-display interval comes.

Abstract: A media processing method for performing media processing by causing a processor to execute plural program modules, including: a first step of controlling input/output of media data, determining at least one call time, and calling a second program module in a second layer at each determined call time, by executing a first program module in a first layer, the first layer being higher than the second layer; a second step of calling at least one third program module in a third layer, the third layer being lower than the second layer, by executing the second program module in the second layer; and a third step of causing the processor to perform data conversion on the media data, the data conversion being an element of the media processing, by executing the third program module in the third layer.

Abstract: When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract: When a branch instruction is decoded by the instruction decoders 409a-409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract: When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract: When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract: A program conversion apparatus converts an input program into a program operable by a processor using a cache memory and outputs the converted program. The program conversion apparatus includes a target region extraction section for extracting from regions of a memory, as a target region, a region in which writing is performed before reading during execution of the input program, and a cache entry specification section for inserting a cache entry specification instruction to add an entry to the cache memory before an instruction to execute a write access to the target region.

Abstract: A processor which decodes and executes an instruction sequence includes: a state hold unit for holding, when a predetermined instruction is executed, a renewal state for an execution result of the predetermined instruction; an obtaining unit for obtaining an instruction sequence composed of instructions matching instructions assigned to an instruction set of the processor, where the instruction set is assigned first conditional instructions, a first state condition for a first conditional instruction being mutually exclusive with a second state condition for a second conditional instruction which has a same operation code as the first conditional instruction, the instruction set not being assigned the second conditional instruction, and the first state condition and the second state condition specifying either of one state and a plurality of states; a decoding unit for decoding each instruction in the obtained instruction sequence one by one; a judging unit for judging whether the renewal state is included in

Abstract: When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract: According to program converting step S100 of the present invention, classes whose objects are created out of the classes included in a program are detected and the result is recorded in an analysis information storing section 12 at an object analyzing step S104, functions (unnecessary functions) regarding classes whose objects are not created are analyzed in accordance with information held in the analysis information storing section 12 and the result is recorded in the analysis information storing section 12 at an unnecessary function analyzing step S105, and definitions of the unnecessary functions are deleted in accordance with information held in the analysis information storing section 12 at an unnecessary function deleting step S106.

Abstract: The information processing device having a SIMD operator includes: a SIMD processing division means for receiving a SIMD instruction from a machine language program and outputting the SIMD instruction repeatedly by a predetermined number of times; a memory address conversion means for converting the memory address of a SIMD instruction related to memory access output from the SIMD processing division means according to the number of times of repetition of the SIMD instruction and outputting the results to the SIMD operator; and a register switch means having a group of registers for the SIMD operator for switching the group of registers to be used by the SIMD operator according to the number of times of repetition of the SIMD instruction.

Abstract: In a program processing procedure specially designed to perform compilation for parallel processing purposes, a method and system for increasing the program execution rate of a target machine is provided. A compiler front end translates source code into intermediate code that has been divided into basic blocks. A parallelizer converts the intermediate code, which has been generated by the compiler front end, into a parallelly executable form. An execution order determiner determines the order of the basic blocks to be executed. An expanded basic block parallelizer subdivides the intermediate code, which has already been divided into the basic blocks, into execution units, each of which is made up of parallelly executable instructions, following the order determined and on the basic block basis.

Abstract: Each of registers R0 to R31 is divided into the upper 32-bit area and the lower 32-bit area. A register writing control unit 431 outputs information to the selectors 4321 and 4322 on the registers and the locations (upper and lower areas) in which data is written by the instructions that have issued in one cycle. Each of the selectors 4321 and 4322 selects one out of pieces of data that have been output from first, second, and third arithmetic operation units 44, 45, and 46 and writes the selected data in the upper or lower area in one register. A dependency analysis unit 110 in a compiling apparatus considers the upper and lower registers in one 64-bit register as separate resources, analyzes the data dependency relations between the instructions, and generates a dependency graph that indicates the data dependency relations. A instruction rearrangement unit 111 rearranges the instructions and generates execution codes using the dependency graph.

Abstract: Each of registers R0 to R31 is divided into the upper 32-bit area and the lower 32-bit area. A register writing control unit 431 outputs information to the selectors 4321 and 4322 on the registers and the locations (upper and lower areas) in which data is written by the instructions that have issued in one cycle. Each of the selectors 4321 and 4322 selects one out of pieces of data that have been output from first, second, and third arithmetic operation units 44, 45, and 46 and writes the selected data in the upper or lower area in one register. A dependency analysis unit 110 in a compiling apparatus considers the upper and lower registers in one 64-bit register as separate resources, analyzes the data dependency relations between the instructions, and generates a dependency graph that indicates the data dependency relations. A instruction rearrangement unit 111 rearranges the instructions and generates execution codes using the dependency graph.

Abstract: A processor can decode short instructions with a word length equal to one unit field and long instructions with a word length equal to two unit fields. An opcode of each kind of instruction is arranged into the first unit field assigned to the instruction. The number of instructions to be executed by the processor in parallel is s. When the ratio of short to long instructions is s-1:1, the s-1 short instructions are assigned to the first unit field to the s-1tA unit field in the parallel execution code, and the long instruction is assigned to the sth unit field to the (s+k?1)th unit field in the same parallel execution code.