Abstract: A parallel data processing system is provided for increasing the program execution rate of a target machine. A parallelizer converts intermediate code, which has been generated by a compiler front end, into a parallelly executable form. An execution order determiner determines the order of the basic blocks to be executed. An expanded basic block parallelizer subdivides the intermediate code of the basic blocks into execution units, each of which is made up of parallelly executable instructions, following the order determined and on the basic block basis. When a particular one of the basic blocks is subdivided into execution units, an instruction belonging to the first execution unit of the next basic block, which has already been subdivided into execution units, is also used.

Abstract: An instruction string optimization apparatus is provided which estimates the size of a constant to be resolved as an address difference before linking instructions. The apparatus comprises code dividing means (202) for dividing a serial assembler code (201) into basic blocks, size dependence relation generation means (204) for analyzing size dependence relations among the sizes of the instruction string between basic blocks, estimation order determining means (206) for determining the order of basic blocks in which the size of a constant to be resolved as an address difference is determined and size determining means (208) for determining the size of the constant in each basic block according to the determined order, whereby the size of a constant to be resolved as an address difference can be estimated to be a value close to and not less than its actual size, the number of codes can be reduced, and the process speed by a linker can be improved.

Abstract: Processor and instruction conversion apparatus, including a technique for reducing the number of types of instructions and processor hardware scale when conditional instructions are used. The processor includes a stare hold unit, an obtaining unit, a decoding unit, a judging unit, and an execution unit. The judging unit judges whether a state hold unit renewal state is included in either of the state and the plurality of states specified by the first state condition in the first conditional instruction when decoded by the decoding unit. When the judgment is affirmative, the execution unit executes an operation specified by the operation code in the first conditional instruction decoded by the decoding unit. The instruction set is assigned first conditional instructions with a first state condition which is mutually exclusive with a second state condition for an unassigned second conditional instruction, both having the same operation code.

Abstract: Each of registers R0 to R31 is divided into the upper 32-bit area and the lower 32-bit area. A register writing control unit 431 outputs information to the selectors 4321 and 4322 on the registers and the locations (upper and lower areas) in which data is written by the instructions that have issued in one cycle. Each of the selectors 4321 and 4322 selects one out of pieces of data that have been output from first, second, and third arithmetic operation units 44, 45, and 46 and writes the selected data in the upper or lower area in one register. A dependency analysis unit 110 in a compiling apparatus considers the upper and lower registers in one 64-bit register as separate resources, analyzes the data dependency relations between the instructions, and generates a dependency graph that indicates the data dependency relations. A instruction rearrangement unit 111 rearranges the instructions and generates execution codes using the dependency graph.

Abstract: Each of registers R0 to R31 is divided into the upper 32-bit area and the lower 32-bit area. A register writing control unit 431 outputs information to the selectors 4321 and 4322 on the registers and the locations (upper and lower areas) in which data is written by the instructions that have issued in one cycle. Each of the selectors 4321 and 4322 selects one out of pieces of data that have been output from first, second, and third arithmetic operation units 44, 45, and 46 and writes the selected data in the upper or lower area in one register. A dependency analysis unit 110 in a compiling apparatus considers the upper and lower registers in one 64-bit register as separate resources, analyzes the data dependency relations between the instructions, and generates a dependency graph that indicates the data dependency relations. A instruction rearrangement unit 111 rearranges the instructions and generates execution codes using the dependency graph.

Abstract: When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract: When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract: When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract: A program conversion apparatus includes: the constant division unit 12 for specifying instructions in the serial assembler code 42 that use large constants which cannot be arranged within the operation fields of object VLIWs and for dividing the specified instructions into divided constant use instructions for storing pieces of the large constants into the specialized constant buffer 107 of a VLIW processor and divided constant use instructions for performing operations using the stored constants; the dependence graph generation unit 20 for generating a dependence graph based on the execution order of each instruction in the serial assembler code 42 after the division process by the constant division unit 12; and the instruction relocation unit 21 for relocating the instructions according to the dependence graph to generate parallel assembler code.

Abstract: A processor can decode short instructions with a word length equal to one unit field and long instructions with a word length equal to two unit fields. An opcode of each kind of instruction is arranged into the first unit field assigned to the instruction. The number of instructions to be executed by the processor in parallel is s. When the ratio of short to long instructions is s-1:1, the s-1 short instructions are assigned to the first unit field to the s-1th unit field in the parallel execution code, and the long instruction is assigned to the sth unit field to the (s+k−1)th unit field in the same parallel execution code.

Abstract: In an optimization apparatus embedded in a compiler apparatus that compiles a high-level language program to a machine language program, equivalence relations among a plurality of expressions are analyzed in a short time period by calculating an equivalent expression set group of each basic block, the equivalent expression set group being composed of equivalent expression sets with equivalence relations. Specifically, an equivalent expression set group at the entry point of a basic block is calculated from equivalent expression set groups at the exit points of basic blocks that precede the basic block, and then an equivalent expression set group at the exit point of the basic block is calculated from the equivalent expression set group at the entry point of the basic block. These calculations are repeated until there are no more changes to the equivalent expression set group at the exit point of any of the basic blocks.

Abstract: A debugging support apparatus for a processor that executes a plurality of instructions in parallel displays lines of source code statements in a user program that are executed in parallel. Code execution unit 15 executes the program. When execution of the program is interrupted at a breakpoint set in advance at a line of a source code statement, user interface unit 11 searches parallel execution information storage unit 5 for lines to be executed in parallel with the line set the breakpoint, and displays a source code statement of the line set the breakpoint and source code statements of the lines to be executed in parallel. As a result, a user is able to visually recognize which lines of source code statements are executed in parallel.

Abstract: Internal variables generated by a compiler are assigned to machine resources such as registers and memory by the resource assigning unit 11, and when the assembler code generation unit 18 has outputted an instruction sequence, the alias accessibility analyzing unit 19 registers memory access instructions in the instruction sequence in the assigned resource information 14 according to whether the instructions have a possibility of access by alias. The assembler code optimization unit 20 refers to the assigned resource information 14 and performs optimization at assembler level, thereby reducing the program size and execution time of the instruction sequence.

Abstract: A processor which decodes and executes an instruction sequence includes: a state hold unit for holding, when a predetermined instruction is executed, a renewal state for an execution result of the predetermined instruction; an obtaining unit for obtaining an instruction sequence composed of instructions matching instructions assigned to an instruction set of the processor, where the instruction set is assigned first conditional instructions, a first state condition for a first conditional instruction being mutually exclusive with a second state condition for a second conditional instruction which has a same operation code as the first conditional instruction, the instruction set not being assigned the second conditional instruction, and the first state condition and the second state condition specifying either of one state and a plurality of states; a decoding unit for decoding each instruction in the obtained instruction sequence one by one; a judging unit for judging whether the renewal state is included in

Abstract: An instruction conversion apparatus and method for converting instruction sequences not including conditional instructions into instruction sequences including conditional instructions wherein the conditional instructions include both a condition and an operation code for execution by the processor when the condition is satisfied. An obtaining unit receives an instruction sequence that does not include a conditional instruction whereby an instruction sequence detection unit detects a conversion target instruction sequence which transfers different transfer objects to the same storage resource when a predetermined condition is satisfied. A judging unit judges whether the instruction set of a specialized processor is assigned a conditional instruction including the same condition as the precondition whereby a conversion unit can then convert the conversion target instruction sequence into the instruction sequence including a conditional instruction with the predetermined condition.

Abstract: A processor for executing operations based on instructions includes an operation constant register 361, a branching constant register 362, a decoding unit 20 for decoding an instruction stored in an instruction register 10, a constant register control unit 32, and an execution unit 30. When the decoding unit 20 finds that the instruction includes a constant to be stored in the branching constant register 362, the constant register control unit 32 shifts a present value in the branching constant register 362 and inserts the constant to be stored, thereby storing a new constant in the branching constant register 362. When the decoding unit 20 finds that a constant is to be stored in the operation constant register 361, the constant register control unit 32 shifts the present value in the operation constant register 361 and inserts the constant to be stored, thereby storing a new constant in the operation constant register 361.

Abstract: A processor for decoding and executing an instruction includes: an instruction register 10 for storing an instruction; a format decoder 21 for decoding a format code located in the P0.0 field 11 of the instruction stored in the instruction register 10; a constant storage unit including a storage region; a constant register control unit 32 which, when the format decoder 21 has referred to the format code and decoded that an operation field includes a constant to be stored in the constant register 36, transfers the constant from the instruction register 10 to the constant storage unit 36; and a constant register output unit 41 which, when the format decoder 21 has referred to the format code and decoded that an operation field includes an operation code showing an operation that should be executed and a piece of an operand that should be used for the operation, links the constant stored in the constant register 36 with the piece of the operand.

Abstract: An optimization apparatus is provided for removing hazards from a program by rearranging instructions for each program segment. The apparatus comprises: a Directed Acyclic Graph (DAG) generating means for generating DAGs for each program segment; a hazard marking means for marking hazard-including combinations of a parent instruction and a child instruction in the DAGs for hazard; and a rearranging means for rearranging the instructions for each program segment so that instructions are inserted between the instructions of each marked combination, wherein the inserted instructions do not destroy values stored in resources used by the instructions of the marked combination.

Abstract: The definition and use information of a constant hold variable are caused to be stored in a constant hold variable information hold unit 6 by a constant hold variable definition detection unit 7 and a use expression detection unit 8. A partial constant expression rewrite unit 9 rewrites to a constant a constant hold variable which, when a variable is rewritten to a constant, allows an expression containing the variable to be convoluted into a constant. A cost judgement and rewrite unit 10 judges by a cost whether the variable is to be used with loading it in a register or constant propagation is to be conducted, and, if constant propagation is to be conducted, rewrites the variable with a constant. A resource allocation unit 11 allocates the variable to a resource. A memory variable rewrite unit 12 rewrites a constant hold variable allocated to a memory to a constant value. A constant hold variable definition removal unit 13 removes the definition of a constant hold variable which becomes unnecessary.

Abstract: A resource assigning apparatus which generates assignments which are combinations of variables and their respective live ranges, which investigates, for each assignment, other assignments with live ranges which interfere or which are continuous and which calculates assigning priority levels. Next, the assigning resource element determination unit assigns each assignment to an assignable resource element starting with the assignment with the highest priority level, in doing so taking into account the use cost which is the cost incurred by the parts of the program which use an assignment and the resource succession relations, thereby calculating a profit value which standardizes an evaluation of a reduction in transfer instructions in the object code and assigning assignments to resource elements with a lowest use cost and highest profit value. In this way, by thoroughly investigating the relations between assignments which allow assigning to a same resource element, a more optimal assigning result is attained.