Patents by Inventor Kensuke Yamaguchi

Kensuke Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9768270
    Abstract: Undesirable metal contamination from a selective metal deposition process can be minimized or eliminated by employing a first material layer on a bevel and a back side of a substrate, while providing a second material layer only on a front side of the substrate. The first material layer and the second material layer are selected such that a selective deposition process of a metal material provides a metal material portion only on the second material layer, while no deposition occurs on the first material layer or isolated islands of the metal material are formed on the first material layer. Any residual metal material can be removed from the bevel and the back side by a wet etch to reduce or prevent metal contamination from the deposited metal material.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: September 19, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Marika Gunji-Yoneoka, Atsushi Suyama, Kensuke Yamaguchi, Hiroyuki Kinoshita, Raghuveer S. Makala, Rahul Sharangpani, Shigehisa Inoue, Tuan Pham
  • Publication number: 20170236746
    Abstract: Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.
    Type: Application
    Filed: September 23, 2016
    Publication date: August 17, 2017
    Inventors: Jixin YU, Zhenyu LU, Hiroyuki OGAWA, Daxin MAO, Kensuke YAMAGUCHI, Sung Tae LEE, Yao-sheng LEE, Johann ALSMEIER
  • Patent number: 9716101
    Abstract: Techniques for forming 3D memory arrays are disclosed. Memory openings are filled with a sacrificial material, such as silicon or nitride. Afterwards, a replacement technique is used to remove nitride from an ONON stack and replace it with a conductive material such as tungsten. Afterwards, memory cell films are formed in the memory openings. The conductive material serves as control gates of the memory cells. The control gate will not suffer from corner rounding. ONON shrinkage is avoided, which will prevent control gate shrinkage. Block oxide between the charge storage region and control gate may be deposited after control gate replacement, so the uniformity is good. Block oxide may be deposited after control gate replacement, so TiN adjacent to control gates can be thicker to prevent fluorine attacking the insulator between adjacent control gates. Therefore, control gate to control gate shorting is prevented.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: July 25, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Zhenyu Lu, Hiro Kinoshita, Daxin Mao, Johann Alsmeier, Wenguang Shi, Yingda Dong, Henry Chien, Kensuke Yamaguchi, Xiaolong Hu
  • Patent number: 9601508
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of a memory opening, all surfaces of the memory opening are provided as silicon oxide surfaces by formation of at least one silicon oxide portion. A silicon nitride layer is formed in the memory opening. After formation of a memory stack structure, backside recesses can be formed employing the silicon oxide portions as an etch stop. The silicon oxide portions can be subsequently removed employing the silicon nitride layer as an etch stop. Physically exposed portions of the silicon nitride layer can be removed selective to the memory stack structure. Damage to the outer layer of the memory stack structure can be minimized or eliminated by successive use of etch stop structures. Electrically conductive layers can be subsequently formed in the backside recesses.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: March 21, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jongsun Sel, Chan Park, Atsushi Suyama, Frank Yu, Hiroyuki Ogawa, Ryoichi Honma, Kensuke Yamaguchi, Hiroaki Iuchi, Naoki Takeguchi, Tuan Pham, Kiyohiko Sakakibara, Jiao Chen
  • Patent number: 9553100
    Abstract: A method of forming a three-dimensional memory device includes forming a stack of alternating first and second material layers over a substrate, forming a memory opening through the stack, forming a memory film and a semiconductor channel in the memory opening, and forming backside recesses by removing the second material layers selective to the first material layers and the memory film, where an outer sidewall of the memory film is physically exposed within each backside recess. The method also includes forming at least one set of surfaces selected from silicon deposition inhibiting surfaces on the first material layers and silicon deposition promoting surfaces over the memory film in the back side recesses, selectively growing a silicon-containing semiconductor portion laterally within each backside recess, forming at least one blocking dielectric within the backside recesses, and forming conductive material layers by depositing a conductive material within the backside recesses.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: January 24, 2017
    Assignee: SANDISK TECHOLOGIES LLC
    Inventors: Hiroyuki Kamiya, Kensuke Yamaguchi
  • Publication number: 20160343718
    Abstract: Techniques for forming 3D memory arrays are disclosed. Memory openings are filled with a sacrificial material, such as silicon or nitride. Afterwards, a replacement technique is used to remove nitride from an ONON stack and replace it with a conductive material such as tungsten. Afterwards, memory cell films are formed in the memory openings. The conductive material serves as control gates of the memory cells. The control gate will not suffer from corner rounding. ONON shrinkage is avoided, which will prevent control gate shrinkage. Block oxide between the charge storage region and control gate may be deposited after control gate replacement, so the uniformity is good. Block oxide may be deposited after control gate replacement, so TiN adjacent to control gates can be thicker to prevent fluorine attacking the insulator between adjacent control gates. Therefore, control gate to control gate shorting is prevented.
    Type: Application
    Filed: October 30, 2015
    Publication date: November 24, 2016
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Zhenyu Lu, Hiro Kinoshita, Daxin Mao, Johann Alsmeier, Wenguang Shi, Yingda Dong, Henry Chien, Kensuke Yamaguchi, Xiaolong Hu
  • Publication number: 20160315095
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of a memory opening, all surfaces of the memory opening are provided as silicon oxide surfaces by formation of at least one silicon oxide portion. A silicon nitride layer is formed in the memory opening. After formation of a memory stack structure, backside recesses can be formed employing the silicon oxide portions as an etch stop. The silicon oxide portions can be subsequently removed employing the silicon nitride layer as an etch stop. Physically exposed portions of the silicon nitride layer can be removed selective to the memory stack structure. Damage to the outer layer of the memory stack structure can be minimized or eliminated by successive use of etch stop structures. Electrically conductive layers can be subsequently formed in the backside recesses.
    Type: Application
    Filed: October 23, 2015
    Publication date: October 27, 2016
    Inventors: Jongsun Sel, Chan Park, Atsushi Suyama, Frank Yu, Hiroyuki Ogawa, Ryoichi Honma, Kensuke Yamaguchi, Hiroaki Iuchi, Naoki Takeguchi, Tuan Pham, Kiyohiko Sakakibara, Jiao Chen
  • Patent number: 9368601
    Abstract: A fabrication process for a vertical channel transistor provides a desired control gate-to-drain overlap and sufficient isolation between the control gate and an underlying metal line. A body of the transistor is formed on a metal line, such as in a pillar shape. The metal line is oxidized to form metal oxide regions having an expanded volume. A gate insulator material and a control gate material are then deposited. The resulting structure is etched to form separate control gates for each transistor, and to expose the metal oxide. A further etch is performed to remove the metal oxide, forming voids under and around the control gates. An insulation fills the voids. An example implementation is a vertical bit line memory device in which the transistors connect a vertical bit line to a horizontal bit line.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: June 14, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Michiaki Sano, Kensuke Yamaguchi, Akira Nakada, Naohito Yanagida
  • Publication number: 20160163725
    Abstract: A method of forming a three-dimensional memory device includes forming a stack of alternating first and second material layers over a substrate, forming a memory opening through the stack, forming a memory film and a semiconductor channel in the memory opening, and forming backside recesses by removing the second material layers selective to the first material layers and the memory film, where an outer sidewall of the memory film is physically exposed within each backside recess. The method also includes forming at least one set of surfaces selected from silicon deposition inhibiting surfaces on the first material layers and silicon deposition promoting surfaces over the memory film in the back side recesses, selectively growing a silicon-containing semiconductor portion laterally within each backside recess, forming at least one blocking dielectric within the backside recesses, and forming conductive material layers by depositing a conductive material within the backside recesses.
    Type: Application
    Filed: December 4, 2014
    Publication date: June 9, 2016
    Inventors: Hiroyuki KAMIYA, Kensuke YAMAGUCHI
  • Publication number: 20160111439
    Abstract: A method of minimizing an overetch or damage to a semiconductor surface underneath a memory opening is provided. A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A sacrificial liner is formed over the first blocking dielectric layer. An opening is formed through a horizontal portion of the sacrificial liner. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched through the opening in the sacrificial liner. A semiconductor surface of the substrate can be physically exposed at a bottom of the memory opening with minimal overetch and/or surface damage. A second blocking dielectric layer can be formed, before or after formation of the sacrificial liner, to provide a multilayer blocking dielectric.
    Type: Application
    Filed: October 21, 2014
    Publication date: April 21, 2016
    Inventors: Masanori Tsutsumi, Hiroshi Sasaki, Hiroyuki Ogawa, Michiaki Sano, Masato Miyamoto, Kensuke Yamaguchi, Seiji Shimabukuro
  • Patent number: 9305937
    Abstract: A method of minimizing an overetch or damage to a semiconductor surface underneath a memory opening is provided. A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A sacrificial liner is formed over the first blocking dielectric layer. An opening is formed through a horizontal portion of the sacrificial liner. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched through the opening in the sacrificial liner. A semiconductor surface of the substrate can be physically exposed at a bottom of the memory opening with minimal overetch and/or surface damage. A second blocking dielectric layer can be formed, before or after formation of the sacrificial liner, to provide a multilayer blocking dielectric.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: April 5, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Masanori Tsutsumi, Hiroshi Sasaki, Hiroyuki Ogawa, Michiaki Sano, Masato Miyamoto, Kensuke Yamaguchi, Seiji Shimabukuro
  • Publication number: 20150380419
    Abstract: Undesirable metal contamination from a selective metal deposition process can be minimized or eliminated by employing a first material layer on a bevel and a back side of a substrate, while providing a second material layer only on a front side of the substrate. The first material layer and the second material layer are selected such that a selective deposition process of a metal material provides a metal material portion only on the second material layer, while no deposition occurs on the first material layer or isolated islands of the metal material are formed on the first material layer. Any residual metal material can be removed from the bevel and the back side by a wet etch to reduce or prevent metal contamination from the deposited metal material.
    Type: Application
    Filed: August 31, 2015
    Publication date: December 31, 2015
    Inventors: Marika GUNJI-YONEOKA, Atusushi SUYAMA, Kensuke YAMAGUCHI, Hiroyuki KINOSHITA, Raghuveer S. MAKALA, Rahul SHARANGPANI, Shigehisa INOUE, Tuan PHAM
  • Publication number: 20150249143
    Abstract: A fabrication process for a vertical channel transistor provides a desired control gate-to-drain overlap and sufficient isolation between the control gate and an underlying metal line. A body of the transistor is formed on a metal line, such as in a pillar shape. The metal line is oxidized to form metal oxide regions having an expanded volume. A gate insulator material and a control gate material are then deposited. The resulting structure is etched to form separate control gates for each transistor, and to expose the metal oxide. A further etch is performed to remove the metal oxide, forming voids under and around the control gates. An insulation fills the voids. An example implementation is a vertical bit line memory device in which the transistors connect a vertical bit line to a horizontal bit line.
    Type: Application
    Filed: February 28, 2014
    Publication date: September 3, 2015
    Applicant: SanDisk 3D LLC
    Inventors: Michiaki Sano, Kensuke Yamaguchi, Akira Nakada, Naohito Yanagida
  • Patent number: 6901685
    Abstract: A method for drying washed objects which is capable of drying the objects in a reduced period of time, effectively preventing contamination of the objects, and preventing energy loss. The apparatus for carrying on the method of drying washed objects includes a drying tank having an opening on the upper portion thereof so that the washed objects can be placed or taken out from above, and a rinsing tank formed integrally with the drying tank, and is capable of being sealed hermetically by closing an openable and closable lid. The drying tank includes a mist-straightening vane for supplying organic solvent mist at normal temperatures to the washed objects, so that the washed objects are dried by organic solvent mist emitted from the mist-straightening vane.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: June 7, 2005
    Assignee: Kaijo Corporation
    Inventors: Kensuke Yamaguchi, Yoshinori Ishikawa, Ki Han
  • Publication number: 20040226185
    Abstract: A method for drying washed objects which is capable of drying the objects in a reduced period of time, effectively preventing contamination of the objects, and preventing energy loss. The apparatus for carrying on the method of drying washed objects includes a drying tank having an opening on the upper portion thereof so that the washed objects can be placed or taken out from above, and a rinsing tank formed integrally with the drying tank, and is capable of being sealed hermetically by closing an openable and closable lid. The drying tank includes a mist-straightening vane for supplying organic solvent mist at normal temperatures to the washed objects, so that the washed objects are dried by organic solvent mist emitted from the mist-straightening vane.
    Type: Application
    Filed: October 24, 2003
    Publication date: November 18, 2004
    Applicant: KAIJO CORPORATION
    Inventors: Kensuke Yamaguchi, Yoshinori Ishikawa, Ki Han
  • Patent number: 6779534
    Abstract: An apparatus and a method for drying washed objects being capable of drying the objects in a reduced period of time, effectively preventing contamination of the objects, and preventing energy loss are provided. The apparatus for drying washed objects includes a drying tank having an opening on the upper portion thereof so that the washed objects can be placed or taken out from above, and a rinsing tank formed integrally with the drying tank, and is capable of being sealed hermetically by closing the openable and closable lid. The drying tank includes a mist-straightening vane for supplying organic solvent mist at normal temperatures to the washed objects, so that the washed objects are dried by organic solvent mist emitted from the mist-straightening vane.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: August 24, 2004
    Assignee: Kaijo Corporation
    Inventors: Kensuke Yamaguchi, Yoshinori Ishikawa, Ki Han
  • Publication number: 20030168086
    Abstract: An apparatus and a method for drying washed objects being capable of drying the objects in a reduced period of time, effectively preventing contamination of the objects, and preventing energy loss are provided. The apparatus for drying washed objects includes a drying tank having an opening on the upper portion thereof so that the washed objects can be placed or taken out from above, and a rinsing tank formed integrally with the drying tank, and is capable of being sealed hermetically by closing the openable and closable lid. The drying tank includes a mist-straightening vane for supplying organic solvent mist at normal temperatures to the washed objects, so that the washed objects are dried by organic solvent mist emitted from the mist-straightening vane.
    Type: Application
    Filed: September 4, 2002
    Publication date: September 11, 2003
    Applicant: KAIJO CORPORATION
    Inventors: Kensuke Yamaguchi, Yoshinori Ishikawa, Ki Han