Patents by Inventor Kentaro Miura
Kentaro Miura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12176438Abstract: According to one embodiment, a semiconductor device includes an oxide semiconductor. The oxide semiconductor includes a first edge portion and a second edge portion intersecting a gate electrode, a first area overlapping the gate electrode, a second area along the first edge portion, a third area along the second edge portion, a fourth area the first edge portion, a fifth area along the second edge portion, a sixth area surrounded by the first area, the second area and the third area, and a seventh area surrounded by the first area, the fourth area and the fifth area. The first area, the second area and the third area, the fourth area and the fifth area have a higher resistivity than those of the sixth area and the seventh area.Type: GrantFiled: December 14, 2021Date of Patent: December 24, 2024Assignee: JAPAN DISPLAY INC.Inventors: Hajime Watakabe, Kentaro Miura, Toshinari Sasaki, Takeshi Sakai, Akihiro Hanada, Masashi Tsubuku
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Patent number: 12148840Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a first insulating layer above a polycrystalline silicon semiconductor, forming an oxide semiconductor on the first insulating layer, forming a second insulating layer on the oxide semiconductor, forming contact holes penetrating to the polycrystalline silicon semiconductor in insulating layers including the first insulating layer and the second insulating layer, forming a metal film on the second insulating layer, forming a patterned resist on the metal film, etching the metal film using the resist as a mask, performing ion implantation into the oxide semiconductor without removing the resist, and removing the resist.Type: GrantFiled: December 6, 2021Date of Patent: November 19, 2024Assignee: JAPAN DISPLAY INC.Inventors: Kentaro Miura, Hajime Watakabe, Ryo Onodera
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Publication number: 20240361687Abstract: A nozzle unit for a liquid treatment apparatus that performs a liquid treatment on a substrate using a liquid, includes a first gas nozzle having a discharge flow path for allowing a first gas to flow through the discharge flow path and a first discharge port for discharging the first gas flowing through the discharge flow path toward a surface of the substrate, wherein the first discharge port is formed so as to extend in a first direction along the surface, and wherein a width of the discharge flow path in the first direction increases as the discharge flow path approaches the first discharge port, so that the first gas is discharged radially from the first discharge port.Type: ApplicationFiled: July 11, 2024Publication date: October 31, 2024Inventors: Takuya MIURA, Kouichirou TANAKA, Shogo TAKAHASHI, Yusuke MIYAKUBO, Kentaro YOSHIHARA
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Patent number: 12108627Abstract: A display device includes a first transistor having a first semiconductor layer, in which a first source region includes a first region in contact with a first source electrode, and a first drain region includes a second region in contact with a first drain electrode. The first source and drain regions, the first region, and the second region each include a first impurity element. In a region close to an interface between the first semiconductor layer and a first insulating layer, a concentration of the first impurity element included in the first and second regions is higher than a concentration of the first impurity element included in the first source region and the first drain region. A method of manufacturing a display device includes forming a first gate electrode and a light shielding layer on a first insulating layer, and forming a second semiconductor layer on the light shielding layer.Type: GrantFiled: November 23, 2021Date of Patent: October 1, 2024Assignee: JAPAN DISPLAY INC.Inventors: Akihiro Hanada, Kentaro Miura, Hajime Watakabe, Ryo Onodera
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Patent number: 12072625Abstract: A nozzle unit for a liquid treatment apparatus that performs a liquid treatment on a substrate using a liquid, includes a first gas nozzle having a discharge flow path for allowing a first gas to flow through the discharge flow path and a first discharge port for discharging the first gas flowing through the discharge flow path toward a surface of the substrate, wherein the first discharge port is formed so as to extend in a first direction along the surface, and wherein a width of the discharge flow path in the first direction increases as the discharge flow path approaches the first discharge port, so that the first gas is discharged radially from the first discharge port.Type: GrantFiled: April 23, 2021Date of Patent: August 27, 2024Assignee: TOKYO ELECTRON LIMITEDInventors: Takuya Miura, Kouichirou Tanaka, Shogo Takahashi, Yusuke Miyakubo, Kentaro Yoshihara
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Publication number: 20230292551Abstract: A display device includes a light-emitting element; a first transistor and a second transistor connected in series between the light-emitting element and a driving power line; a third transistor electrically connected to a gate electrode of the first transistor; and a fourth transistor connected in parallel between a drain electrode of the first transistor and the light-emitting element, wherein a ratio of a channel width W1 to a channel length L1 of the first transistor (a W1/L1 ratio) and a ratio of a channel width W2 to a channel length L2 of the second transistor (a W2/L2 ratio) are larger than a ratio of a channel width W3 to a channel length L3 of the third transistor (a W3/L3 ratio) and a ratio of a channel width W4 to a channel length L4 of the fourth transistor (a W4/L4 ratio).Type: ApplicationFiled: March 1, 2023Publication date: September 14, 2023Applicant: Japan Display Inc.Inventors: Masashi TSUBUKU, Takeshi SAKAI, Kentaro MIURA, Hajime WATAKABE, Takaya TAMARU, Hiroshi TABATAKE, Yutaka UMEDA
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Publication number: 20230169922Abstract: A display device including a substrate, a light-emitting element, a first transistor, and a second transistor, the first transistor including the first gate electrode on the substrate; a first insulating film on the first gate electrode, a first oxide semiconductor on the first insulating film, and having an area overlapping the first gate electrode, a second insulating film on the first oxide semiconductor, and a first conductive layer on the second insulating film, the second transistor including the first insulating film on the substrate, a second oxide semiconductor on the first insulating film, a second insulating film on the first oxide semiconductor and the second oxide semiconductor, and having a thickness smaller than a thickness of the first insulating film, a second gate electrode on the second insulating film, and having an area overlapping the second oxide semiconductor.Type: ApplicationFiled: February 1, 2023Publication date: June 1, 2023Applicant: Japan Display Inc.Inventors: Hajime WATAKABE, Kentaro MIURA, Masashi TSUBUKU
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Patent number: 11660982Abstract: In a fuel cell vehicle and a method of controlling the fuel cell vehicle, when a gas pressure in a high pressure tank becomes less than a first threshold pressure, the SOC of an energy storage device is increased to a margin SOC. When the gas pressure becomes a second threshold pressure which is lower than the first threshold pressure, the amount of fuel released from the high pressure tank is limited to prevent the occurrence of buckling, and limit the travel driving force by the motor to a required limit. At the time of limiting the travel driving force, electrical energy of the energy storage device is used to provide assistance in a manner that the travel driving force by the motor becomes the travel driving force of the required limit.Type: GrantFiled: December 3, 2020Date of Patent: May 30, 2023Assignee: Honda Motor Co., Ltd.Inventors: Satoru Kawase, Toshihiko Kanezaki, Kentaro Miura, Kazuo Miyagawa, Kazuyuki Kadowaki
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Publication number: 20230108412Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer including a source area, a drain area and a channel area, a first insulating layer, an etching stopper layer located immediately above the channel area and being thinner than the first insulating layer, a second insulating layer provided on the etching stopper layer and being thicker than the first insulating layer, a gate electrode, a third insulating layer which covers the etching stopper layer, the second insulating layer and the gate electrode and covers the first insulating layer immediately above the source area and immediately above the drain area, a source electrode in contact with the source area, and a drain electrode in contact with the drain area.Type: ApplicationFiled: October 3, 2022Publication date: April 6, 2023Applicant: Japan Display Inc.Inventors: Hajime WATAKABE, Masashi TSUBUKU, Kentaro MIURA, Akihiro HANADA, Takaya TAMARU
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Publication number: 20220367691Abstract: According to one embodiment, a method of manufacturing a semiconductor device, includes forming a first insulating layer, an oxide semiconductor layer, a second insulating layer, a buffer layer and a metal layer sequentially on a base, forming a patterned resist on the metal layer, etching the buffer layer and the metal layer using the resist as a mask to expose an upper surface of the second insulating layer, reducing a volume of the resist to expose an upper surface along a side surface of the metal layer, etching the metal layer using the resist as a mask, to form a gate electrode and to expose an upper surface of the buffer layer, and carrying out ion implantation on the oxide semiconductor layer using the gate electrode as a mask.Type: ApplicationFiled: April 26, 2022Publication date: November 17, 2022Applicant: Japan Display Inc.Inventors: Hajime WATAKABE, Masashi TSUBUKU, Kentaro MIURA, Akihiro HANADA, Takaya TAMARU
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Publication number: 20220238558Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a polycrystalline silicon semiconductor, an oxide semiconductor, a gate electrode located directly above the oxide semiconductor, a first conductive layer in contact with the polycrystalline silicon semiconductor via a first contact hole, and in contact with the oxide semiconductor via a second contact hole and a second conductive layer stacked on the first conductive layer between the first contact hole and the second contact hole. The first conductive layer includes an extending portion extending from the second contact hole toward the gate electrode. The second conductive layer is not stacked on the extending portion. The first conductive layer is thinner than the second conductive layer.Type: ApplicationFiled: January 25, 2022Publication date: July 28, 2022Applicant: Japan Display Inc.Inventors: Hajime WATAKABE, Kentaro MIURA, Akihiro HANADA
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Publication number: 20220231149Abstract: According to one embodiment, a method of manufacturing a semiconductor device comprises forming an oxide semiconductor layer, forming a gate insulating layer in contact with the oxide semiconductor layer and covering the oxide semiconductor layer, and forming a gate electrode on the gate insulating layer so as to overlap the oxide semiconductor layer, and injecting boron through the gate electrode and the gate insulating layer after forming the gate electrode, wherein a boron concentration included in a region of the gate insulating layer overlapping the gate electrode is in a range of 1E+16 [atoms/cm3] or more.Type: ApplicationFiled: January 14, 2022Publication date: July 21, 2022Applicant: Japan Display Inc.Inventors: Akihiro HANADA, Kentaro MIURA, Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU, Takeshi SAKAI
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Publication number: 20220190164Abstract: According to one embodiment, a semiconductor device includes an oxide semiconductor. The oxide semiconductor includes a first edge portion and a second edge portion intersecting a gate electrode, a first area overlapping the gate electrode, a second area along the first edge portion, a third area along the second edge portion, a fourth area the first edge portion, a fifth area along the second edge portion, a sixth area surrounded by the first area, the second area and the third area, and a seventh area surrounded by the first area, the fourth area and the fifth area. The first area, the second area and the third area, the fourth area and the fifth area have a higher resistivity than those of the sixth area and the seventh area.Type: ApplicationFiled: December 14, 2021Publication date: June 16, 2022Applicant: Japan Display Inc.Inventors: Hajime WATAKABE, Kentaro MIURA, Toshinari SASAKI, Takeshi SAKAI, Akihiro HANADA, Masashi TSUBUKU
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Publication number: 20220181493Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a first insulating layer above a polycrystalline silicon semiconductor, forming an oxide semiconductor on the first insulating layer, forming a second insulating layer on the oxide semiconductor, forming contact holes penetrating to the polycrystalline silicon semiconductor in insulating layers including the first insulating layer and the second insulating layer, forming a metal film on the second insulating layer, forming a patterned resist on the metal film, etching the metal film using the resist as a mask, performing ion implantation into the oxide semiconductor without removing the resist, and removing the resist.Type: ApplicationFiled: December 6, 2021Publication date: June 9, 2022Applicant: Japan Display Inc.Inventors: Kentaro MIURA, Hajime WATAKABE, Ryo ONODERA
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Publication number: 20220165826Abstract: According to one embodiment, in a display device, a first transistor includes a first semiconductor layer, in which a first source region includes a first region in contact a the first source electrode and a first drain region includes a second region in contact with a first drain electrode, the first source and drain regions, the first region, and the second region each include a first impurity element, and, in a region close to an interface between the first semiconductor layer and a first insulating layer, a concentration of the first impurity element included in the first and second regions is higher than a concentration of the first impurity element included in the first source region and the first drain region.Type: ApplicationFiled: November 23, 2021Publication date: May 26, 2022Applicant: Japan Display Inc.Inventors: Akihiro HANADA, Kentaro MIURA, Hajime WATAKABE, Ryo ONODERA
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Publication number: 20220013796Abstract: A fuel cell system for a vehicle includes a plurality of unit fuel cell groups, which are connected, each of unit fuel cell groups including a hydrogen tank, a fuel cell and a fuel cell controller configured to control power generation of the fuel cell, a tank controller configured to control filling and discharge of hydrogen in the hydrogen tank of each of at least two of the unit fuel cell groups, each of the unit fuel cell groups includes a hydrogen supply line configured to bring hydrogen to the fuel cell, the hydrogen supply lines of the at least two unit fuel cell groups are linked with each other, and the tank controller stops supply of hydrogen into the fuel cell of a unit fuel cell group in which an abnormality has been detected.Type: ApplicationFiled: July 2, 2021Publication date: January 13, 2022Inventors: Daishi Igarashi, Satoru Kawase, Kentaro Miura, Shinji Matsunaga
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Patent number: 11086418Abstract: A control device is provided that is intended to be used for navigating between and within pages of a graphic user interface on a computer monitor. The top shell of the device is intended to rotated with respect to the bottom shell for scrolling and by pressing down on the top shell a selection can be made.Type: GrantFiled: December 30, 2016Date of Patent: August 10, 2021Assignee: DOUZEN, INC.Inventors: Kentaro Miura, Julian Orbanes
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Publication number: 20210170912Abstract: In a fuel cell vehicle and a method of controlling the fuel cell vehicle, when a gas pressure in a high pressure tank becomes less than a first threshold pressure, the SOC of an energy storage device is increased to a margin SOC. When the gas pressure becomes a second threshold pressure which is lower than the first threshold pressure, the amount of fuel released from the high pressure tank is limited to prevent the occurrence of buckling, and limit the travel driving force by the motor to a required limit. At the time of limiting the travel driving force, electrical energy of the energy storage device is used to provide assistance in a manner that the travel driving force by the motor becomes the travel driving force of the required limit.Type: ApplicationFiled: December 3, 2020Publication date: June 10, 2021Inventors: Satoru KAWASE, Toshihiko KANEZAKI, Kentaro MIURA, Kazuo MIYAGAWA, Kazuyuki KADOWAKI
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Patent number: 10714629Abstract: According to one embodiment, a transistor includes first to third conductors, first and second oxide semiconductors, and a gate insulating film. The first and second conductors are stacked via an insulator above a substrate. The first oxide semiconductor is formed on the first conductor. The second oxide semiconductor is formed on the first oxide semiconductor. The second oxide semiconductor have a pillar shape through the second conductor along a first direction crossing a surface of the substrate. The second oxide semiconductor is different from the first oxide semiconductor. The gate insulating film is formed between the second conductor and the second oxide semiconductor. The third conductor is formed on the second oxide semiconductor.Type: GrantFiled: September 5, 2018Date of Patent: July 14, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Nobuyoshi Saito, Tomomasa Ueda, Kentaro Miura, Keiji Ikeda, Tsutomu Tezuka
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Patent number: 10553601Abstract: According to one embodiment, a memory includes: a member extending in a first direction and including an oxide semiconductor layer including first to third portions arranged in order from the bit line to the source line; first, second and third conductive layers arranged along the first direction and facing the first to third portions, respectively, the first conductive layer including first material, and each of the second and third conductive layer including a second material different from the first material; a memory cell in a first position corresponding to the first portion, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor in a second position corresponding to the second portion; and a second transistor in a third position corresponding to the third portion.Type: GrantFiled: July 20, 2018Date of Patent: February 4, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tsutomu Tezuka, Fumitaka Arai, Keiji Ikeda, Tomomasa Ueda, Nobuyoshi Saito, Chika Tanaka, Kentaro Miura, Tomoaki Sawabe