Patents by Inventor Kentaro Miura

Kentaro Miura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250113543
    Abstract: A semiconductor device according to an embodiment of the present invention includes an oxide semiconductor layer having a polycrystalline structure and including an impurity region containing an impurity element, a gate electrode over the oxide semiconductor layer, an insulating layer between the oxide semiconductor layer and the gate electrode, a first contact hole penetrating the insulating layer and exposing the impurity region, a second contact hole penetrating at least the insulating layer and having a greater depth than the first contact hole, and a connection wiring electrically connecting the impurity region to a layer which is exposed in the second contact hole through the first contact hole and the second contact hole. The connection wiring includes a first conductive layer and a second conductive layer on the first conductive layer. A portion of the first conductive layer that is exposed from the second conductive layer contains the impurity element.
    Type: Application
    Filed: September 25, 2024
    Publication date: April 3, 2025
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Kentaro MIURA, Akihiro HANADA, Masahiro WATABE
  • Publication number: 20250113709
    Abstract: A display device includes a light-emitting element, a first transistor, and a second transistor, the first transistor includes a first gate electrode, a first insulating film, a first oxide semiconductor layer, a second insulating film, and a first conductive layer provided on the second insulating film, and the second transistor includes the first insulating film, a second oxide semiconductor layer, a second insulating film, and a second gate electrode, wherein an etching rate of the first oxide semiconductor layer and the second semiconductor layer is less than 3 nm/min when the first oxide semiconductor layer and the second semiconductor layer are etched using an etching solution containing phosphoric acid as a main component at 40° C.
    Type: Application
    Filed: September 25, 2024
    Publication date: April 3, 2025
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Kentaro MIURA, Masahiro WATABE
  • Publication number: 20250113542
    Abstract: A semiconductor device comprises a first insulating layer; an oxide semiconductor layer having a polycrystalline structure on the first insulating layer; a gate insulating layer on the semiconductor oxide layer; a buffer layer on the gate insulating layer; a gate wiring on the buffer layer; and a second insulating layer on the gate wiring. The oxide semiconductor layer has a first region, a second region and a third region aligned toward a first direction. An electrical resistivity of the second region is higher than an electrical resistivity of the first region and lower than an electrical resistivity of the third region. A sheet resistance of the third region is less than 1000 ohm/square.
    Type: Application
    Filed: September 17, 2024
    Publication date: April 3, 2025
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Kentaro MIURA, Akihiro HANADA, Takaya TAMARU, Masahiro WATABE
  • Publication number: 20250113544
    Abstract: A semiconductor device according to an embodiment of the present invention includes: an oxide semiconductor layer; a first gate electrode facing the oxide semiconductor layer; a first gate insulating layer between the oxide semiconductor layer and the first gate electrode; an electrode arranged in a region overlapping the oxide semiconductor layer in a plan view and electrically connected to the oxide semiconductor layer; and a metal nitride layer between the oxide semiconductor layer and the electrode, wherein the oxide semiconductor layer is polycrystalline, and an etching rate of the oxide semiconductor layer with respect to an etchant containing phosphoric acid as a main component is less than 3 nm/min at 40° C.
    Type: Application
    Filed: September 25, 2024
    Publication date: April 3, 2025
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Kentaro MIURA, Masahiro WATABE
  • Publication number: 20250113546
    Abstract: A semiconductor device includes a gate electrode, an oxide semiconductor layer having a polycrystalline structure, and a gate insulating layer between the gate electrode and the oxide semiconductor layer. The oxide semiconductor layer includes a source region and a drain region each containing an impurity element, a channel region between the source region and the drain region, and a first region adjacent to the channel region. The first region includes a first edge extending along a first direction travelling from the source region to the drain region. The first region has a higher electrical resistivity than each of the source region and the drain region. An etching rate of the oxide semiconductor layer is less than 3 nm/min when the oxide semiconductor layer is etched using an etching solution containing phosphoric acid as a main component at 40° C.
    Type: Application
    Filed: September 26, 2024
    Publication date: April 3, 2025
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Kentaro MIURA, Takeshi SAKAI, Akihiro HANADA, Masahiro WATABE
  • Publication number: 20250113618
    Abstract: A semiconductor device according to an embodiment of the present invention includes: a first semiconductor layer; a first gate electrode; a first gate insulating layer; a first insulating layer above the first gate electrode; a first electrode overlapping the first semiconductor layer, and electrically connected to the first semiconductor layer; a second semiconductor layer above the first insulating layer and made of a different material from the first semiconductor layer; a second gate electrode; a second gate insulating layer; a second electrode overlapping the second semiconductor layer, and electrically connected to the second semiconductor layer; and a first metal nitride layer between the second semiconductor layer and the second electrode, wherein the second semiconductor layer is polycrystalline, and an etching rate of the second semiconductor layer with respect to an etchant including phosphoric acid as a main component is less than 3 nm/min at 40° C.
    Type: Application
    Filed: September 17, 2024
    Publication date: April 3, 2025
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Kentaro MIURA, Masahiro WATABE
  • Patent number: 12176438
    Abstract: According to one embodiment, a semiconductor device includes an oxide semiconductor. The oxide semiconductor includes a first edge portion and a second edge portion intersecting a gate electrode, a first area overlapping the gate electrode, a second area along the first edge portion, a third area along the second edge portion, a fourth area the first edge portion, a fifth area along the second edge portion, a sixth area surrounded by the first area, the second area and the third area, and a seventh area surrounded by the first area, the fourth area and the fifth area. The first area, the second area and the third area, the fourth area and the fifth area have a higher resistivity than those of the sixth area and the seventh area.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: December 24, 2024
    Assignee: JAPAN DISPLAY INC.
    Inventors: Hajime Watakabe, Kentaro Miura, Toshinari Sasaki, Takeshi Sakai, Akihiro Hanada, Masashi Tsubuku
  • Patent number: 12148840
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a first insulating layer above a polycrystalline silicon semiconductor, forming an oxide semiconductor on the first insulating layer, forming a second insulating layer on the oxide semiconductor, forming contact holes penetrating to the polycrystalline silicon semiconductor in insulating layers including the first insulating layer and the second insulating layer, forming a metal film on the second insulating layer, forming a patterned resist on the metal film, etching the metal film using the resist as a mask, performing ion implantation into the oxide semiconductor without removing the resist, and removing the resist.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: November 19, 2024
    Assignee: JAPAN DISPLAY INC.
    Inventors: Kentaro Miura, Hajime Watakabe, Ryo Onodera
  • Patent number: 12108627
    Abstract: A display device includes a first transistor having a first semiconductor layer, in which a first source region includes a first region in contact with a first source electrode, and a first drain region includes a second region in contact with a first drain electrode. The first source and drain regions, the first region, and the second region each include a first impurity element. In a region close to an interface between the first semiconductor layer and a first insulating layer, a concentration of the first impurity element included in the first and second regions is higher than a concentration of the first impurity element included in the first source region and the first drain region. A method of manufacturing a display device includes forming a first gate electrode and a light shielding layer on a first insulating layer, and forming a second semiconductor layer on the light shielding layer.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: October 1, 2024
    Assignee: JAPAN DISPLAY INC.
    Inventors: Akihiro Hanada, Kentaro Miura, Hajime Watakabe, Ryo Onodera
  • Publication number: 20230292551
    Abstract: A display device includes a light-emitting element; a first transistor and a second transistor connected in series between the light-emitting element and a driving power line; a third transistor electrically connected to a gate electrode of the first transistor; and a fourth transistor connected in parallel between a drain electrode of the first transistor and the light-emitting element, wherein a ratio of a channel width W1 to a channel length L1 of the first transistor (a W1/L1 ratio) and a ratio of a channel width W2 to a channel length L2 of the second transistor (a W2/L2 ratio) are larger than a ratio of a channel width W3 to a channel length L3 of the third transistor (a W3/L3 ratio) and a ratio of a channel width W4 to a channel length L4 of the fourth transistor (a W4/L4 ratio).
    Type: Application
    Filed: March 1, 2023
    Publication date: September 14, 2023
    Applicant: Japan Display Inc.
    Inventors: Masashi TSUBUKU, Takeshi SAKAI, Kentaro MIURA, Hajime WATAKABE, Takaya TAMARU, Hiroshi TABATAKE, Yutaka UMEDA
  • Publication number: 20230169922
    Abstract: A display device including a substrate, a light-emitting element, a first transistor, and a second transistor, the first transistor including the first gate electrode on the substrate; a first insulating film on the first gate electrode, a first oxide semiconductor on the first insulating film, and having an area overlapping the first gate electrode, a second insulating film on the first oxide semiconductor, and a first conductive layer on the second insulating film, the second transistor including the first insulating film on the substrate, a second oxide semiconductor on the first insulating film, a second insulating film on the first oxide semiconductor and the second oxide semiconductor, and having a thickness smaller than a thickness of the first insulating film, a second gate electrode on the second insulating film, and having an area overlapping the second oxide semiconductor.
    Type: Application
    Filed: February 1, 2023
    Publication date: June 1, 2023
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Kentaro MIURA, Masashi TSUBUKU
  • Patent number: 11660982
    Abstract: In a fuel cell vehicle and a method of controlling the fuel cell vehicle, when a gas pressure in a high pressure tank becomes less than a first threshold pressure, the SOC of an energy storage device is increased to a margin SOC. When the gas pressure becomes a second threshold pressure which is lower than the first threshold pressure, the amount of fuel released from the high pressure tank is limited to prevent the occurrence of buckling, and limit the travel driving force by the motor to a required limit. At the time of limiting the travel driving force, electrical energy of the energy storage device is used to provide assistance in a manner that the travel driving force by the motor becomes the travel driving force of the required limit.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: May 30, 2023
    Assignee: Honda Motor Co., Ltd.
    Inventors: Satoru Kawase, Toshihiko Kanezaki, Kentaro Miura, Kazuo Miyagawa, Kazuyuki Kadowaki
  • Publication number: 20230108412
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer including a source area, a drain area and a channel area, a first insulating layer, an etching stopper layer located immediately above the channel area and being thinner than the first insulating layer, a second insulating layer provided on the etching stopper layer and being thicker than the first insulating layer, a gate electrode, a third insulating layer which covers the etching stopper layer, the second insulating layer and the gate electrode and covers the first insulating layer immediately above the source area and immediately above the drain area, a source electrode in contact with the source area, and a drain electrode in contact with the drain area.
    Type: Application
    Filed: October 3, 2022
    Publication date: April 6, 2023
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Kentaro MIURA, Akihiro HANADA, Takaya TAMARU
  • Publication number: 20220367691
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device, includes forming a first insulating layer, an oxide semiconductor layer, a second insulating layer, a buffer layer and a metal layer sequentially on a base, forming a patterned resist on the metal layer, etching the buffer layer and the metal layer using the resist as a mask to expose an upper surface of the second insulating layer, reducing a volume of the resist to expose an upper surface along a side surface of the metal layer, etching the metal layer using the resist as a mask, to form a gate electrode and to expose an upper surface of the buffer layer, and carrying out ion implantation on the oxide semiconductor layer using the gate electrode as a mask.
    Type: Application
    Filed: April 26, 2022
    Publication date: November 17, 2022
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Masashi TSUBUKU, Kentaro MIURA, Akihiro HANADA, Takaya TAMARU
  • Publication number: 20220238558
    Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a polycrystalline silicon semiconductor, an oxide semiconductor, a gate electrode located directly above the oxide semiconductor, a first conductive layer in contact with the polycrystalline silicon semiconductor via a first contact hole, and in contact with the oxide semiconductor via a second contact hole and a second conductive layer stacked on the first conductive layer between the first contact hole and the second contact hole. The first conductive layer includes an extending portion extending from the second contact hole toward the gate electrode. The second conductive layer is not stacked on the extending portion. The first conductive layer is thinner than the second conductive layer.
    Type: Application
    Filed: January 25, 2022
    Publication date: July 28, 2022
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Kentaro MIURA, Akihiro HANADA
  • Publication number: 20220231149
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device comprises forming an oxide semiconductor layer, forming a gate insulating layer in contact with the oxide semiconductor layer and covering the oxide semiconductor layer, and forming a gate electrode on the gate insulating layer so as to overlap the oxide semiconductor layer, and injecting boron through the gate electrode and the gate insulating layer after forming the gate electrode, wherein a boron concentration included in a region of the gate insulating layer overlapping the gate electrode is in a range of 1E+16 [atoms/cm3] or more.
    Type: Application
    Filed: January 14, 2022
    Publication date: July 21, 2022
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Kentaro MIURA, Hajime WATAKABE, Masashi TSUBUKU, Toshinari SASAKI, Takaya TAMARU, Takeshi SAKAI
  • Publication number: 20220190164
    Abstract: According to one embodiment, a semiconductor device includes an oxide semiconductor. The oxide semiconductor includes a first edge portion and a second edge portion intersecting a gate electrode, a first area overlapping the gate electrode, a second area along the first edge portion, a third area along the second edge portion, a fourth area the first edge portion, a fifth area along the second edge portion, a sixth area surrounded by the first area, the second area and the third area, and a seventh area surrounded by the first area, the fourth area and the fifth area. The first area, the second area and the third area, the fourth area and the fifth area have a higher resistivity than those of the sixth area and the seventh area.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 16, 2022
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Kentaro MIURA, Toshinari SASAKI, Takeshi SAKAI, Akihiro HANADA, Masashi TSUBUKU
  • Publication number: 20220181493
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a first insulating layer above a polycrystalline silicon semiconductor, forming an oxide semiconductor on the first insulating layer, forming a second insulating layer on the oxide semiconductor, forming contact holes penetrating to the polycrystalline silicon semiconductor in insulating layers including the first insulating layer and the second insulating layer, forming a metal film on the second insulating layer, forming a patterned resist on the metal film, etching the metal film using the resist as a mask, performing ion implantation into the oxide semiconductor without removing the resist, and removing the resist.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 9, 2022
    Applicant: Japan Display Inc.
    Inventors: Kentaro MIURA, Hajime WATAKABE, Ryo ONODERA
  • Publication number: 20220165826
    Abstract: According to one embodiment, in a display device, a first transistor includes a first semiconductor layer, in which a first source region includes a first region in contact a the first source electrode and a first drain region includes a second region in contact with a first drain electrode, the first source and drain regions, the first region, and the second region each include a first impurity element, and, in a region close to an interface between the first semiconductor layer and a first insulating layer, a concentration of the first impurity element included in the first and second regions is higher than a concentration of the first impurity element included in the first source region and the first drain region.
    Type: Application
    Filed: November 23, 2021
    Publication date: May 26, 2022
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Kentaro MIURA, Hajime WATAKABE, Ryo ONODERA
  • Publication number: 20220013796
    Abstract: A fuel cell system for a vehicle includes a plurality of unit fuel cell groups, which are connected, each of unit fuel cell groups including a hydrogen tank, a fuel cell and a fuel cell controller configured to control power generation of the fuel cell, a tank controller configured to control filling and discharge of hydrogen in the hydrogen tank of each of at least two of the unit fuel cell groups, each of the unit fuel cell groups includes a hydrogen supply line configured to bring hydrogen to the fuel cell, the hydrogen supply lines of the at least two unit fuel cell groups are linked with each other, and the tank controller stops supply of hydrogen into the fuel cell of a unit fuel cell group in which an abnormality has been detected.
    Type: Application
    Filed: July 2, 2021
    Publication date: January 13, 2022
    Inventors: Daishi Igarashi, Satoru Kawase, Kentaro Miura, Shinji Matsunaga