Patents by Inventor Kentaro Wada

Kentaro Wada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240072441
    Abstract: According to one embodiment, an antenna device includes a substrate; a feed element provided on or inside the substrate; a feeder line provided on or inside the substrate and configured to feed power to the feed element; and at least one of a director provided on or inside the substrate and away from the feed element, and a reflector provided on or inside the substrate and away from the feed element, wherein the substrate includes a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, at least one of at least a part of the feed element and at least a part of the director is provided on or inside the first portion, and at least a part of the feeder line is provided on or inside the second portion.
    Type: Application
    Filed: February 28, 2023
    Publication date: February 29, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kentaro WADA, Koh HASHIMOTO
  • Publication number: 20240040692
    Abstract: A printed wiring board includes an insulating layer, a conductor layer formed on the insulating layer, an adhesive layer formed on the conductor layer such that the adhesive layer is covering an upper surface and a side surface of the conductor layer, and a resin insulating layer formed on the insulating layer such that the resin insulating layer is covering the conductor layer formed on the insulating layer. The conductor layer is formed such that the upper surface of the conductor layer has an unevenness having a root mean square roughness Rq of 0.23 ?m or less.
    Type: Application
    Filed: July 25, 2023
    Publication date: February 1, 2024
    Applicant: IBIDEN CO., LTD.
    Inventors: Kentaro WADA, Koji KONDO, Kenji KUNIEDA, Masashi UMETSU, Yuta OKAGA
  • Publication number: 20230294141
    Abstract: A cleaning apparatus for cleaning a workpiece includes a holding unit for holding an outer circumferential portion of the workpiece thereon, a rotating mechanism for rotating the holding unit, and a cleaning unit for cleaning a reverse side of the workpiece. The cleaning unit includes a cleaning member for contacting the reverse side of the workpiece and a drive mechanism for moving the cleaning member toward and away from the reverse side of the workpiece.
    Type: Application
    Filed: January 17, 2023
    Publication date: September 21, 2023
    Inventor: Kentaro WADA
  • Publication number: 20230292448
    Abstract: A printed wiring board includes an insulating layer, a first conductor layer formed on the insulating layer, an adhesive layer formed on the first conductor layer, a resin insulating layer formed on the insulating layer such that the adhesive layer is formed between the first conductor layer and the resin insulating layer, and a second conductor layer formed on the resin insulating layer. The first conductor layer is formed such that the first conductor layer has a smooth upper surface and a smooth side surface and that the adhesive layer has a smooth film formed on the smooth upper and side surfaces, and a protruding part protruding from the smooth film.
    Type: Application
    Filed: March 10, 2023
    Publication date: September 14, 2023
    Applicant: IBIDEN CO., LTD.
    Inventors: Kentaro WADA, Koji KONDO
  • Publication number: 20230080335
    Abstract: A printed wiring board includes a resin insulating layer including resin and particles, and a conductor layer formed on a surface of the resin insulating layer. The particles in the resin insulating layer include first particles and second particles such that the first particles are partially embedded in the resin and the second particles are completely embedded in the resin, and the resin insulating layer is formed such that the first particles has exposed surfaces exposed from the resin and covered surfaces covered by the resin, respectively, the surface of the resin insulating layer includes the first exposed surfaces, and a ratio of a second area to a first area is in a range of 0.1 to 0.25 where the first area is an area of the surface of the resin insulating layer, and the second area is obtained by summing areas of the exposed surfaces of the first particles.
    Type: Application
    Filed: August 30, 2022
    Publication date: March 16, 2023
    Applicant: IBIDEN CO., LTD.
    Inventors: Satoru KAWAI, Katsuhiko TANNO, Susumu KAGOHASHI, Kentaro WADA
  • Publication number: 20230020713
    Abstract: A computer-implemented method of estimating a pose of a target object in a three-dimensional scene includes: obtaining image data and associated depth information representing a view of the three-dimensional scene; processing the image data and the associated depth information to generate a volumetric reconstruction for each of a plurality of objects in the three-dimensional scene, including the target object; determining a volumetric grid containing the target object; generating, using the generated volumetric reconstructions, occupancy data indicating portions of the volumetric grid occupied by free space and portions of the volumetric grid occupied by objects other than the target object; and estimating the pose of the target object using the generated occupancy data and pointwise feature data for a plurality of points on a surface of the target object.
    Type: Application
    Filed: September 13, 2022
    Publication date: January 19, 2023
    Inventors: Kentaro WADA, Edgar Antonio SUCAR ESCAMILLA, Stephen Lloyd JAMES, Daniel James LENTON, Andrew DAVISON
  • Publication number: 20230019499
    Abstract: A computer-implemented method of determining a pose of each of a plurality of objects includes, for each given object: using image data and associated depth information to estimate a pose of the given object. The method includes iteratively updating the estimated poses by: sampling, for each given object, a plurality of points from a predetermined model of the given object transformed in accordance with the estimated pose of the given object; determining first occupancy data for each given object dependent on positions of the points sampled from the predetermined model, relative to a voxel grid containing the given object; determining second occupancy data for each given object dependent on positions of the points sampled from the predetermined models of the other objects, relative to the voxel grid containing the given object; and updating the estimated poses of the plurality of objects to reduce an occupancy penalty.
    Type: Application
    Filed: September 13, 2022
    Publication date: January 19, 2023
    Inventors: Kentaro WADA, Edgar Antonio SUCAR ESCAMILLA, Stephen Lloyd JAMES, Daniel James LENTON, Andrew DAVISON
  • Patent number: 11538704
    Abstract: A processing method of a workpiece in which the workpiece with a plate shape is processed by using a vacuum chamber is provided. In the processing method of a workpiece, a negative pressure is caused to act on a holding surface from a suction path, and suction holding of the workpiece is executed by a chuck table. Then, the gas pressure in the vacuum chamber is reduced to at least 50 Pa and at most 5000 Pa. Then, while the suction holding of the workpiece is executed, an inert gas in a plasma state is supplied to the workpiece, and voltages are applied to electrodes disposed in the chuck table to execute electrostatic adhesion of the workpiece by the chuck table. Then, a processing gas in a plasma state is supplied, and dry etching of the workpiece is executed.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: December 27, 2022
    Assignee: DISCO CORPORATION
    Inventors: Yoshio Watanabe, Hiroyuki Takahashi, Kentaro Wada
  • Publication number: 20220369456
    Abstract: A wiring substrate includes a first insulating layer, a conductor layer formed on the first insulating layer, a second insulating layer formed on the first insulating layer such that the second insulating layer is covering the conductor layer, and a coating film formed on a surface of the conductor layer such that the coating film is adhering the conductor layer and the second insulating layer. The conductor layer includes a conductor pad and a wiring pattern, and the conductor pad of the conductor layer has a mounting surface including a first region and a component mounting region formed such that the second insulating layer has a through hole exposing the component mounting region and that the first region is covered by the second insulating layer and roughened to have a surface roughness higher than a first surface roughness of a surface of the wiring pattern facing the second insulating layer.
    Type: Application
    Filed: April 27, 2022
    Publication date: November 17, 2022
    Applicant: IBIDEN CO., LTD.
    Inventors: Tomoyuki IKEDA, Kentaro WADA
  • Patent number: 11363719
    Abstract: A wiring substrate includes a core substrate, and a build-up part laminated on the substrate and including resin insulating layers. The insulating layers include a first insulating layer, the build-up part includes a conductor layer on the first insulating layer, a second insulating layer on the first insulating layer and covering the conductor layer, and a recess penetrating through the second insulating layer and exposing portion of the conductor layer such that the conductor layer includes component mounting region that places an electronic component in the recess and a conductor pad forming bottom surface of the recess, the insulating layers include inorganic filler such that all insulating layers or all insulating layers other than the first insulating layer include the inorganic filler and that inorganic filler content rate of the first insulating layer is lower than inorganic filler content rate of the insulating layers other than the first insulating layer.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: June 14, 2022
    Assignee: IBIDEN CO., LTD.
    Inventors: Hiroyasu Noto, Kentaro Wada
  • Publication number: 20220102215
    Abstract: A wafer processing method includes: a resin film coating step of coating an upper surface of a wafer with a water-soluble resin and coating a dicing tape exposed between the wafer and a frame with a water-soluble resin, and solidifying the water-soluble resin to form a resin film, a partial resin film removing step of removing the resin film from regions to be divided of the wafer to partially expose the upper surface of the wafer, an etching step of subjecting the regions to be divided of the wafer to plasma etching to divide the wafer into individual device chips, and a whole resin film removing step of cleaning a frame unit to remove wholly the resin film.
    Type: Application
    Filed: September 14, 2021
    Publication date: March 31, 2022
    Inventors: Susumu YOKOO, Hiroyuki TAKAHASHI, Kentaro WADA, Yoshio WATANABE, Kenji OKAZAKI, Yoshiteru NISHIDA
  • Patent number: 11171009
    Abstract: There is provided a processing method of a wafer. The processing method includes a frame unit preparation step of fixing the wafer in an opening of an annular frame by an adhesion tape to prepare a frame unit and a frame unit holding step of attracting and holding the wafer of the frame unit by an chuck table in an etching chamber with the intermediary of the adhesion tape. The processing method includes also a shielding step of covering the annular frame and (or) an annular region of the adhesion tape by a cover member to shield the annular frame and (or) the annular region from an external space and a dry etching step of supplying a gas to the etching chamber and executing dry etching for the wafer after execution of the frame unit holding step and the shielding step.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: November 9, 2021
    Assignee: DISCO CORPORATION
    Inventors: Hiroyuki Takahashi, Kentaro Wada, Yoshio Watanabe, Susumu Yokoo
  • Publication number: 20210282266
    Abstract: A wiring substrate includes a core substrate, and a build-up part laminated on the substrate and including resin insulating layers. The insulating layers include a first insulating layer, the build-up part includes a conductor layer on the first insulating layer, a second insulating layer on the first insulating layer and covering the conductor layer, and a recess penetrating through the second insulating layer and exposing portion of the conductor layer such that the conductor layer includes component mounting region that places an electronic component in the recess and a conductor pad forming bottom surface of the recess, the insulating layers include inorganic filler such that all insulating layers or all insulating layers other than the first insulating layer include the inorganic filler and that inorganic filler content rate of the first insulating layer is lower than inorganic filler content rate of the insulating layers other than the first insulating layer.
    Type: Application
    Filed: February 25, 2021
    Publication date: September 9, 2021
    Applicant: IBIDEN CO., LTD.
    Inventors: Hiroyasu NOTO, Kentaro WADA
  • Publication number: 20210268621
    Abstract: A fine adjustment thread assembly couples a first part and a second part to each other while keeping the first part and the second part spaced apart, adjusts the distance between the first part and the second part, and detects a load applied to the second part. The assembly includes first external threads that can be brought into threaded engagement with first internal threads formed in the first part, second external threads that are axially spaced from the first external threads, that have a thread pitch different from that of the first internal thread, and that can be brought into threaded engagement with second internal threads formed in the second part. A joint portion between the first external threads and the second external threads houses a load sensor under a compressive load.
    Type: Application
    Filed: February 22, 2021
    Publication date: September 2, 2021
    Inventors: Toshiyasu RIKIISHI, Kentaro WADA
  • Publication number: 20210090926
    Abstract: A processing method of a workpiece in which the workpiece with a plate shape is processed by using a vacuum chamber is provided. In the processing method of a workpiece, a negative pressure is caused to act on a holding surface from a suction path, and suction holding of the workpiece is executed by a chuck table. Then, the gas pressure in the vacuum chamber is reduced to at least 50 Pa and at most 5000 Pa. Then, while the suction holding of the workpiece is executed, an inert gas in a plasma state is supplied to the workpiece, and voltages are applied to electrodes disposed in the chuck table to execute electrostatic adhesion of the workpiece by the chuck table. Then, a processing gas in a plasma state is supplied, and dry etching of the workpiece is executed.
    Type: Application
    Filed: September 17, 2020
    Publication date: March 25, 2021
    Inventors: Yoshio WATANABE, Hiroyuki TAKAHASHI, Kentaro WADA
  • Publication number: 20210028022
    Abstract: There is provided a processing method of a wafer. The processing method includes a frame unit preparation step of fixing the wafer in an opening of an annular frame by an adhesion tape to prepare a frame unit and a frame unit holding step of attracting and holding the wafer of the frame unit by an chuck table in an etching chamber with the intermediary of the adhesion tape. The processing method includes also a shielding step of covering the annular frame and (or) an annular region of the adhesion tape by a cover member to shield the annular frame and (or) the annular region from an external space and a dry etching step of supplying a gas to the etching chamber and executing dry etching for the wafer after execution of the frame unit holding step and the shielding step.
    Type: Application
    Filed: July 16, 2020
    Publication date: January 28, 2021
    Inventors: Hiroyuki TAKAHASHI, Kentaro WADA, Yoshio WATANABE, Susumu YOKOO
  • Patent number: 8997589
    Abstract: A rack buffer unit 8 serving as a sample-container switching unit is provided between a rack conveying module 4 and a rack conveying module 5 which convey racks 2 on which the sample containers 1 are mounted, and an urgent-sample loading module 7 installing a rack 2 on which a sample container 1 storing a sample desired to be preferentially analyzed is mounted is provided. The rack 2 which is in the process of sample dispensing and the rack 2 desired to be preferentially analyzed are switched from each other by the rack buffer unit 8, and the sample container 1 mounted on the rack 2 desired to be preferentially analyzed is moved to a sample dispensing position in a short period of time.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: April 7, 2015
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Hidenobu Komatsu, Katsuhiro Kambara, Tetsuji Kawahara, Kentaro Wada
  • Patent number: 8278108
    Abstract: An automatic analyzer of the type equipped with a sample preprocessing function pretreats a desired sample in a pretreating unit before pipetting the sample into an analyzing unit for analysis. When all samples are carried to the analyzing unit via the pretreating unit, irrespective of whether the sample is to be pretreated, this causes loss in terms of both costs and installation space requirements. In the case where the preprocessing is required, a minimal quantity of the sample is also necessary in order to make the sample react to the preprocessing liquid. In addition, the possible presence of a residual sample left in the pretreating unit could affect analytical results. The automatic analyzer which includes an analyzing unit and a pretreating unit further includes a sample-pipetting mechanism constructed to have a function that allows the mechanism to access a plurality of pipetting positions without a sample sucking/discharging position being fixed.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: October 2, 2012
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Kentaro Wada, Katsuhiro Kambara, Tetsuji Kawahara, Hidenobu Komatsu
  • Publication number: 20110283779
    Abstract: An automatic analyzer of the type equipped with a sample preprocessing function pretreats a desired sample in a pretreating unit before pipetting the sample into an analyzing unit for analysis. When all samples are carried to the analyzing unit via the pretreating unit, irrespective of whether the sample is to be pretreated, this causes loss in terms of both costs and installation space requirements. In the case where the preprocessing is required, a minimal quantity of the sample is also necessary in order to make the sample react to the preprocessing liquid. In addition, the possible presence of a residual sample left in the pretreating unit could affect analytical results. The automatic analyzer which includes an analyzing unit and a pretreating unit further includes a sample-pipetting mechanism constructed to have a function that allows the mechanism to access a plurality of pipetting positions without a sample sucking/discharging position being fixed.
    Type: Application
    Filed: January 22, 2010
    Publication date: November 24, 2011
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Kentaro Wada, Katsuhiro Kambara, Tetsuji Kawahara, Hidenobu Komatsu
  • Publication number: 20110271773
    Abstract: A rack buffer unit 8 serving as a sample-container switching unit is provided between a rack conveying module 4 and a rack conveying module 5 which convey racks 2 on which the sample containers 1 are mounted, and an urgent-sample loading module 7 installing a rack 2 on which a sample container 1 storing a sample desired to be preferentially analyzed is mounted is provided. The rack 2 which is in the process of sample dispensing and the rack 2 desired to be preferentially analyzed are switched from each other by the rack buffer unit 8, and the sample container 1 mounted on the rack 2 desired to be preferentially analyzed is moved to a sample dispensing position in a short period of time.
    Type: Application
    Filed: January 25, 2010
    Publication date: November 10, 2011
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Hidenobu Komatsu, Katsuhiro Kambara, Tetsuji Kawahara, Kentaro Wada