Abstract: An information processing device has a digital-to-pulse converter which outputs a pulse signal including a pulse having a pulse length in accordance with a digital input signal, and a selective oscillator which performs an oscillation operation while the pulse of the pulse signal is output and holds an oscillation operation state at a point of time where the output of the pulse is stopped.

Abstract: Amplifier circuitry has sampling circuitry which samples an input voltage, a quantizer which quantizes an output voltage of the sampling circuitry and outputs an output code, a differential amplifier which amplifies a differential voltage between the output voltage of the sampling circuitry and a reference voltage and performs offset adjustment according to the output code of the quantizer, and a first capacitor which is connected between an output node of the differential amplifier and an output node of the sampling circuitry.

Abstract: An analog-to-digital converter has a switched capacitor comprising a capacitor to perform charging and discharging by switching a switch, the switched capacitor varying a charge amount of the capacitor in accordance with a frequency of an oscillation signal in accordance with a differential signal between an input signal and a feedback signal, capacitance of the capacitor, and a predetermined bias voltage, a feedback signal generator to generate the feedback signal based on an output signal of the switched capacitor, and a digital converter to generate a digital signal by digital conversion of the input signal based on the oscillation signal.

Abstract: An information processing device has a digital-to-pulse converter which outputs a pulse signal including a pulse having a pulse length in accordance with a digital input signal, and a selective oscillator which performs an oscillation operation while the pulse of the pulse signal is output and holds an oscillation operation state at a point of time where the output of the pulse is stopped.

Abstract: A successive approximation register (SAR) analog-to-digital converter includes a first capacitance digital-to-analog converter (CDAC), a first comparator configured to compare a voltage of an output signal from the first CDAC with a reference voltage, a first SAR circuit configured to control the first CDAC based on an output of the first comparator, a second CDAC to which the output signal from the first CDAC is input, a second comparator configured to compare a voltage of an output signal from the second CDAC with a reference voltage, a second SAR circuit configured to control the second CDAC based on an output of the second comparator and generate a digital signal representing a residual voltage of the output signal of the first CDAC, and a feedback circuit configured to delay the digital signal, generate a residual signal from the delayed digital signal, and output the residual signal to the first CDAC.

Abstract: A successive approximation register (SAR) analog-to-digital converter includes a first capacitance digital-to-analog converter (CDAC), a first comparator configured to compare a voltage of an output signal from the first CDAC with a reference voltage, a first SAR circuit configured to control the first CDAC based on an output of the first comparator, a second CDAC to which the output signal from the first CDAC is input, a second comparator configured to compare a voltage of an output signal from the second CDAC with a reference voltage, a second SAR circuit configured to control the second CDAC based on an output of the second comparator and generate a digital signal representing a residual voltage of the output signal of the first CDAC, and a feedback circuit configured to delay the digital signal, generate a residual signal from the delayed digital signal, and output the residual signal to the first CDAC.

Abstract: A reference current generating circuit has a variable current supply to output a reference current, delay circuitry to generate a reference clock by delaying a clock by a reference delay amount and a delay clock by delaying the clock depending on a current value of the reference current, a phase comparator to compare a phase of the reference clock with a phase of the delay clock to output a comparison result, and control circuitry to control the current value of the reference current based on the compared result.

Abstract: An amplifier circuit includes a sampling circuit and an amplifier connected to an output of the sampling circuit. A feedback capacitor is between an output terminal of the amplifier and an output terminal of the sampling circuit. A quantizer that includes a comparator is configured to quantize a voltage at the output terminal of the sampling circuit according to a comparison of a voltage at the output terminal of the sampling circuit to a voltage at the reference potential terminal of the comparator. The quantizer outputs a digital code according to the voltage comparison. A control circuit receives the digital code from the quantizer and stores the digital code in a register as a cancellation digital code. A digital-analog (D/A) converter outputs an analog signal in accordance with digital codes from the control circuit.

Abstract: A successive approximation register analog-to-digital converter includes a capacitance digital-to-analog converter (CDAC) having, a voltage storing circuit connected to an output terminal of the CDAC and including a plurality of capacitors connected in parallel, an output voltage of the CDAC being stored in a selected one of the capacitors, a selector configured to output a voltage stored in the selected one of the capacitors, a comparator configured to compare a voltage input to an input terminal thereof, which is connected to an output terminal of the CDAC, with a reference voltage, and a successive approximation register configured to control the CDAC based on an output of the comparator, and cyclically control the voltage storing circuit and the selector, such that the output of the selector is output to the output terminal one or more cycles after the output voltage was stored in the selected one of the capacitors.

Abstract: A reference current generating circuit has a variable current supply to output a reference current, delay circuitry to generate a reference clock by delaying a clock by a reference delay amount and a delay clock by delaying the clock depending on a current value of the reference current, a phase comparator to compare a phase of the reference clock with a phase of the delay clock to output a comparison result, and control circuitry to control the current value of the reference current based on the compared result.

Abstract: A switched capacitor circuit includes a first sampling circuit having a first sampling capacitance element. The first sampling circuit receives an input voltage and outputs a sampled voltage according to a first sampling operation. A quantizer quantizes the sampled voltage output from the first sampling circuit and outputs a quantized value corresponding to the sampled voltage. A digital-to-analog converter outputs an analog signal in accordance with the quantized value from the quantizer. A first logic circuit outputs an instruction to start a sampling operation of a second sampling circuit, which is configured to sample the analog signal output from the digital-to-analog converter, when the quantizer completes quantization of the sampled voltage.

Abstract: An amplifier circuit has a sample-and-hold circuit to sample and hold an input signal, an amplifier which comprises an input terminal inputted with the input signal held by the sample-and-hold circuit and an output terminal outputting an amplification signal obtained by amplifying the input signal inputted, a feedback capacitor to be connected between the input terminal and output terminal of the amplifier, a successive approximation circuit to perform successive approximation operation to correct the amplification signal based on a voltage of the input terminal of the amplifier, the successive approximation operation being performed a predetermined number of cycles, and a control circuit to control the successive approximation circuit based on an amplification error included in the amplification signal.

Abstract: An amplifier circuit has a sample-and-hold circuit to sample and hold an input signal, an amplifier which comprises an input terminal inputted with the input signal held by the sample-and-hold circuit and an output terminal outputting an amplification signal obtained by amplifying the input signal inputted, a feedback capacitor to be connected between the input terminal and output terminal of the amplifier, a successive approximation circuit to perform successive approximation operation to correct the amplification signal based on a voltage of the input terminal of the amplifier, the successive approximation operation being performed a predetermined number of cycles, and a control circuit to control the successive approximation circuit based on an amplification error included in the amplification signal.

Abstract: An A/D converter has an analog input terminal, an analog output terminal, a digital output terminal, a first resistance comprising one end connected to the analog input terminal or a reference voltage line and another end connected to a first node, a second resistance comprising one end connected to the first node and another end connected to the analog output terminal, an operational amplifier comprising a first input terminal connected to the first node, a second input terminal connected to the reference voltage line or the analog input terminal, and an output terminal connected to the analog output terminal, a quantizer comprising an input terminal connected to the analog input terminal and an output terminal connected to the digital output terminal, and a DA converter comprising an input terminal connected to the digital output terminal and an output terminal connected to the first node.

Abstract: An A/D converter circuit has an amplifier circuit to amplify an input signal and output a first amplification signal and a second amplification signal, the second amplification signal having an amplification error smaller than that in the first amplification signal, a first sampling circuit to sample the first amplification signal, a first A/D converter to perform A/D conversion on the first amplification signal sampled by the first sampling circuit and output a first digital signal, a second sampling circuit to sample the second amplification signal, a D/A converter to perform D/A conversion on the first digital signal and output a first analog signal, a subtracter to subtract the first analog signal from the second amplification signal sampled by the second sampling circuit and output a second analog signal, and a second A/D converter to perform A/D conversion on the second analog signal and output a second digital signal.

Abstract: An A/D converter circuit has an amplifier circuit to amplify an input signal and output a first amplification signal and a second amplification signal, the second amplification signal having an amplification error smaller than that in the first amplification signal, a first sampling circuit to sample the first amplification signal, a first A/D converter to perform A/D conversion on the first amplification signal sampled by the first sampling circuit and output a first digital signal, a second sampling circuit to sample the second amplification signal, a D/A converter to perform D/A conversion on the first digital signal and output a first analog signal, a subtracter to subtract the first analog signal from the second amplification signal sampled by the second sampling circuit and output a second analog signal, and a second A/D converter to perform A/D conversion on the second analog signal and output a second digital signal.

Abstract: An A/D converter has an analog input terminal, an analog output terminal, a digital output terminal, a first resistance comprising one end connected to the analog input terminal or a reference voltage line and another end connected to a first node, a second resistance comprising one end connected to the first node and another end connected to the analog output terminal, an operational amplifier comprising a first input terminal connected to the first node, a second input terminal connected to the reference voltage line or the analog input terminal, and an output terminal connected to the analog output terminal, a quantizer comprising an input terminal connected to the analog input terminal and an output terminal connected to the digital output terminal, and a DA converter comprising an input terminal connected to the digital output terminal and an output terminal connected to the first node.

Abstract: An amplifier circuit has a sampling circuit to comprise a sampling capacitor which samples an input voltage and a plurality of switches, a quantizer to quantize an output voltage of the sampling circuit, a DA converter to output an analog signal depending on a quantization signal by the quantizer, and a feedback capacitor to feed the analog signal back to the output voltage of the sampling circuit.

Abstract: An amplifier circuit has a sampling circuit to comprise a sampling capacitor which samples an input voltage and a plurality of switches, a quantizer to quantize an output voltage of the sampling circuit, a DA converter to output an analog signal depending on a quantization signal by the quantizer, and a feedback capacitor to feed the analog signal back to the output voltage of the sampling circuit.

Abstract: A semiconductor device having a bonding pad region, and a method of its fabrication. A conductive layer is formed on an isolation layer separating transistors of the device, to anchor the interconnection layer on the bonding region. The conductive layer may be formed from the same layer of material that gate electrodes of the transistors are formed. An oxide insulation layer covers the conductive layer and has at least one opening exposing the conductive layer in the bonding pad region. A barrier metal layer, formed on the diffusion regions and the insulation layer, extends into the opening where it makes a firm direct connection with the exposed conductive layer. A bonding pad is formed on the barrier metal layer by providing the interconnection layer on the barrier metal layer. Since the conductive layer and the barrier metal layer are firmly connected, and secures the interconnection layer in the bonding pad structure.