Patents by Inventor Kenya SUGIHARA

Kenya SUGIHARA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9455822
    Abstract: A transmitter for transmitting a transmission signal subjected to modulation after error correction coding and a receiver including a phase compensation unit for receiving the transmission signal and performing demodulation therefor while maintaining synchronization thereof and an error correction decoding unit for performing decoding processing for received data that has been subjected to the demodulation. The transmitter transmits a signal formed of a plurality of pilot sequences as a part of the transmission signal, and the receiver has a phase slip estimation processing function for estimating the phase slip by the phase compensation unit by using the plurality of pilot sequences, and for estimating a phase difference component by the error correction decoding unit, to thereby correct a phase of the received data.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: September 27, 2016
    Assignees: Mitsubishi Electric Corporation, Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Wataru Matsumoto, Toshiaki Akino, Yoshikuni Miyata, Kenya Sugihara, Takashi Sugihara, Takafumi Fujimori
  • Patent number: 9438377
    Abstract: A two-reference-point-pair determining unit 101 determines two reference point pairs by selecting two transmission symbol points with their LLR computation target bit being 0 and two transmission symbol points with their LLR computation target bit being 1. An LLR computation unit 113 assigns weights to the two LLRs calculated for the two reference point pairs, respectively, followed by adding them, and further adds to the addition result a correction term that may be zero sometimes, thus computing LLR for the two reference point pairs.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: September 6, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenya Sugihara, Wataru Matsumoto
  • Publication number: 20150365105
    Abstract: A data structure of a check matrix for the error correction code is a data structure of a check matrix for an error correction code, in which the error correction code is the LDPC code, and in which the check matrix has a matrix structure in which rows are rearranged for submatrices consisting of a part of columns of the check matrix. Moreover, in the method and device for varying the coding rate of the error correction code, a puncture position that is determined in accordance with a puncture position determination signal is a puncture position with which a number of columns in which two or more 1s are contained in a region of the check matrix that is directly affected by puncturing is minimized.
    Type: Application
    Filed: February 8, 2013
    Publication date: December 17, 2015
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kenya SUGIHARA, Yoshikuni MIYATA, Wataru MATSUMOTO
  • Patent number: 9081677
    Abstract: An input bit error ratio estimating method executed by a communication control unit includes a computing, a condition determining, a first input BER estimating, a second input BER estimating, a third input BER estimating, and an input BER estimation result outputting. In the condition determining, the communication control unit determines which of a plurality of conditions set in advance to be narrowed down to one has been established, based on a post-internal decoding residual error detection ratio. Based on the condition that is determined in the condition determining as one that has been established, the communication control unit selects one out of a plurality of processing procedures for estimating the input BER, namely, selects one of the first input BER estimating to the third input BER estimating and executes the selected processing.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: July 14, 2015
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yoshikuni Miyata, Kenya Sugihara, Kiyoshi Onohara, Kazuo Kubo, Hideo Yoshida, Takashi Mizuochi
  • Publication number: 20150195081
    Abstract: A transmitter for transmitting a transmission signal subjected to modulation after error correction coding and a receiver including a phase compensation unit for receiving the transmission signal and performing demodulation therefor while maintaining synchronization thereof and an error correction decoding unit for performing decoding processing for received data that has been subjected to the demodulation. The transmitter transmits a signal formed of a plurality of pilot sequences as a part of the transmission signal, and the receiver has a phase slip estimation processing function for estimating the phase slip by the phase compensation unit by using the plurality of pilot sequences, and for estimating a phase difference component by the error correction decoding unit, to thereby correct a phase of the received data.
    Type: Application
    Filed: August 27, 2013
    Publication date: July 9, 2015
    Applicants: MITSUBISHI ELECTRIC CORPORATION, MITSUBISHI ELECTRIC RESEARCH LABORATORIES, INC.
    Inventors: Wataru Matsumoto, Toshiaki Akino, Yoshikuni Miyata, Kenya Sugihara, Takashi Sugihara, Takafumi Fujimori
  • Publication number: 20150188578
    Abstract: An error correction encoding device 1 includes a sparse matrix computing unit 2 that computes exclusive OR of a submatrix, in a parity-check matrix, corresponding to an information bit sequence, and the information bit sequence on the basis of the position of 1 in the submatrix to calculate a vector, a fundamental matrix operator 3 that calculates a predetermined matrix by performing a predetermined fundamental matrix operation on a submatrix, in the parity-check matrix, corresponding to a parity bit sequence, and a matrix multiplier 4 that calculates the parity bit sequence by multiplying the predetermined matrix which the fundamental matrix operator 3 calculates, and the vector which the sparse matrix computing unit 2 calculates.
    Type: Application
    Filed: October 29, 2013
    Publication date: July 2, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kenya Sugihara, Wataru Matsumoto
  • Publication number: 20140310568
    Abstract: A Sum-product decoder 17 carries out soft-decision iterative decoding on a received signal s?(t) received by a signal receiving unit 12 by using an extended check matrix Hd which is a combination of a matrix D in which differential modulation by a differential modulator 3 is replaced by a check matrix and a check matrix H for error correcting codes to carry out error correction decoding on an information sequence bi.
    Type: Application
    Filed: January 15, 2013
    Publication date: October 16, 2014
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Wataru Matsumoto, Yoshikuni Miyata, Kenya Sugihara
  • Publication number: 20140229805
    Abstract: A two-reference-point-pair determining unit 101 determines two reference point pairs by selecting two transmission symbol points with their LLR computation target bit being 0 and two transmission symbol points with their LLR computation target bit being 1. An LLR computation unit 113 assigns weights to the two LLRs calculated for the two reference point pairs, respectively, followed by adding them, and further adds to the addition result a correction term that may be zero sometimes, thus computing LLR for the two reference point pairs.
    Type: Application
    Filed: October 5, 2012
    Publication date: August 14, 2014
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kenya Sugihara, Wataru Matsumoto
  • Patent number: 8631299
    Abstract: An error correction method and device and a communication system using them, including an LDPC code generation method capable of adjusting an encoding rate of an LDPC code in a variable manner while leaving the length of the code constant by use of an efficient encoding method or mechanism supporting a variable encoding rate, so that the encoding rate of the LDPC code can be adjusted without changing the code length. An error correction method includes a row dividing to divide each of a part or all of rows into two or more rows based on one parity check matrix, and a code construction to construct a plurality of LDPC codes with arbitrary code rates, respectively.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: January 14, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenya Sugihara, Hideo Yoshida, Yoshikuni Miyata
  • Patent number: 8601337
    Abstract: In row calculation, a value which is obtained by subtracting an offset according to a minimum of the absolute values of column LLRs from the minimum of the absolute values of the column LLRs is set as a row LLR corresponding to a column of the column LLRs.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: December 3, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenya Sugihara, Yoshikuni Miyata, Hideo Yoshida
  • Publication number: 20130311840
    Abstract: An input bit error ratio estimating method executed by a communication control unit includes a computing, a condition determining, a first input BER estimating, a second input BER estimating, a third input BER estimating, and an input BER estimation result outputting. In the condition determining, the communication control unit determines which of a plurality of conditions set in advance to be narrowed down to one has been established, based on a post-internal decoding residual error detection ratio. Based on the condition that is determined in the condition determining as one that has been established, the communication control unit selects one out of a plurality of processing procedures for estimating the input BER, namely, selects one of the first input BER estimating to the third input BER estimating and executes the selected processing.
    Type: Application
    Filed: February 20, 2012
    Publication date: November 21, 2013
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yoshikuni Miyata, Kenya Sugihara, Kiyoshi Onohara, Kazuo Kubo, Hideo Yoshida, Takashi Mizuochi
  • Publication number: 20120210189
    Abstract: An error correction method and device and a communication system using them, including an LDPC code generation method capable of adjusting an encoding rate of an LDPC code in a variable manner while leaving the length of the code constant by use of an efficient encoding method or mechanism supporting a variable encoding rate, so that the encoding rate of the LDPC code can be adjusted without changing the code length. An error correction method includes a row dividing to divide each of a part or all of rows into two or more rows based on one parity check matrix, and a code construction to construct a plurality of LDPC codes with arbitrary code rates, respectively.
    Type: Application
    Filed: November 11, 2010
    Publication date: August 16, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kenya Sugihara, Hideo Yoshida, Yoshikuni Miyata
  • Publication number: 20100325514
    Abstract: In row calculation, a value which is obtained by subtracting an offset according to a minimum of the absolute values of column LLRs from the minimum of the absolute values of the column LLRs is set as a row LLR corresponding to a column of the column LLRs.
    Type: Application
    Filed: June 18, 2010
    Publication date: December 23, 2010
    Inventors: Kenya SUGIHARA, Yoshikuni Miyata, Hideo Yoshida