Patents by Inventor Kenya Yamashita

Kenya Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230010490
    Abstract: A wavelength beam combining system includes: at least one laser diode bar that includes a plurality of emitters arranged in a row from a first end side to a second end side, and a heating element placed on the second end side with respect to the plurality of emitters; an optical element that condenses beams emitted from the plurality of emitters; a diffraction grating; an external resonance mirror; and a controlling apparatus that controls power supplied to the plurality of emitters and the heating element. The laser diode bar is placed so that a locked wavelength for an emitter located on the second end side is longer than the locked wavelength for an emitter located on the first end side. The controlling apparatus controls the power supplied to the heating element so that the heating element has a higher temperature than the plurality of emitters.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 12, 2023
    Inventor: Kenya YAMASHITA
  • Patent number: 11335839
    Abstract: The object of the present invention is to provide a Group III nitride semiconductor light emitting diode having improved light extraction efficiency. A Group III nitride semiconductor light emitting diode according to the present disclosure includes an RAMO4 layer including a single crystal represented by the general formula RAMO4 (wherein R represents one or more trivalent elements selected from the group consisting of Sc, In, Y and lanthanoid elements, A represents one or more trivalent elements selected from the group consisting of Fe (III), Ga and Al, and M represents one or more divalent elements selected from the group consisting of Mg, Mn, Fe (II), Co, Cu, Zn and Cd); and a layered product stacked on the RAMO4 layer. The layered product includes at least a light emitting layer including a Group III nitride semiconductor.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: May 17, 2022
    Assignee: PANASONIC CORPORATION
    Inventors: Hiroshi Ono, Kenya Yamashita, Akihiko Ishibashi
  • Patent number: 10923346
    Abstract: A Group III nitride semiconductor for growing a high-quality crystal having a low defect density and a method for producing the Group III nitride semiconductor. The Group III nitride semiconductor includes an RAMO4 substrate including a single crystal represented by the general formula RAMO4 (where R represents one or more trivalent elements selected from the group consisting of Sc, In, Y and lanthanoid elements, A represents one or more trivalent elements selected from the group consisting of Fe(III), Ga and Al, and M represents one or more divalent elements selected from the group consisting of Mg, Mn, Fe(II), Co, Cu, Zn and Cd); a p-type Group III nitride crystal layer disposed on the RAMO4 substrate; a plurality of n-type Group III nitride crystal layers disposed on the p-type Group III nitride crystal layer; and a Group III nitride crystal layer disposed on the n-type Group III nitride crystal layers.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: February 16, 2021
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Akihiko Ishibashi, Hiroshi Ono, Kenya Yamashita
  • Patent number: 10763395
    Abstract: A flip-chip light emitting diode element capable of reducing lateral resistance. The flip-chip light emitting diode element includes a stacked body structure configured by sequentially stacking a first n-type group III nitride semiconductor layer having a carrier concentration that is at least 1×1019 cm?3 but less than 3×1020 cm?3, a second n-type group III nitride semiconductor layer having a carrier concentration that is at least 5×1017 cm?3 but less than 1×1019 cm?3, a light-emitting layer formed by a group III nitride semiconductor, and a p-type group III nitride semiconductor layer. A height of unevenness on an interface between the first n-type group III nitride semiconductor layer and the second n-type group III nitride semiconductor layer is greater than that of unevenness of an interface between the second n-type group III nitride semiconductor layer and the light emitting layer.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: September 1, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hiroshi Ohno, Kenya Yamashita
  • Publication number: 20200135447
    Abstract: A Group III nitride semiconductor for growing a high-quality crystal having a low defect density and a method for producing the Group III nitride semiconductor. The Group III nitride semiconductor includes an RAMO4 substrate including a single crystal represented by the general formula RAMO4 (where R represents one or more trivalent elements selected from the group consisting of Sc, In, Y and lanthanoid elements, A represents one or more trivalent elements selected from the group consisting of Fe(III), Ga and Al, and M represents one or more divalent elements selected from the group consisting of Mg, Mn, Fe(II), Co, Cu, Zn and Cd); a p-type Group III nitride crystal layer disposed on the RAMO4 substrate; a plurality of n-type Group III nitride crystal layers disposed on the p-type Group III nitride crystal layer; and a Group III nitride crystal layer disposed on the n-type Group III nitride crystal layers.
    Type: Application
    Filed: September 6, 2019
    Publication date: April 30, 2020
    Inventors: Akihiko ISHIBASHI, Hiroshi ONO, Kenya YAMASHITA
  • Publication number: 20200014431
    Abstract: The object of the present invention is to provide a Group III nitride semiconductor light emitting diode having improved light extraction efficiency. A Group III nitride semiconductor light emitting diode according to the present disclosure includes an RAMO4 layer including a single crystal represented by the general formula RAMO4 (wherein R represents one or more trivalent elements selected from the group consisting of Sc, In, Y and lanthanoid elements, A represents one or more trivalent elements selected from the group consisting of Fe (III), Ga and Al, and M represents one or more divalent elements selected from the group consisting of Mg, Mn, Fe (II), Co, Cu, Zn and Cd); and a layered product stacked on the RAMO4 layer. The layered product includes at least a light emitting layer including a Group III nitride semiconductor.
    Type: Application
    Filed: July 9, 2019
    Publication date: January 9, 2020
    Applicant: Panasonic Corporation
    Inventors: Hiroshi ONO, Kenya YAMASHITA, Akihiko ISHIBASHI
  • Publication number: 20190348569
    Abstract: A flip-chip light emitting diode element capable of reducing lateral resistance. The flip-chip light emitting diode element includes a stacked body structure configured by sequentially stacking a first n-type group III nitride semiconductor layer having a carrier concentration that is at least 1×1019 cm?3 but less than 3×1020 cm?3, a second n-type group III nitride semiconductor layer having a carrier concentration that is at least 5×1017 cm?3 but less than 1×1019 cm?3, a light-emitting layer formed by a group III nitride semiconductor, and a p-type group III nitride semiconductor layer. A height of unevenness on an interface between the first n-type group III nitride semiconductor layer and the second n-type group III nitride semiconductor layer is greater than that of unevenness of an interface between the second n-type group III nitride semiconductor layer and the light emitting layer.
    Type: Application
    Filed: March 7, 2019
    Publication date: November 14, 2019
    Inventors: HIROSHI OHNO, KENYA YAMASHITA
  • Patent number: 9520344
    Abstract: Included are: the third frame which is electrically connected to the first intermediate frame and is arranged above the first frame; the fourth frame which is electrically connected to the second intermediate frame and is arranged above the second frame; the electric source terminal part which is provided on an extension of the first frame; the ground terminal part which is provided on an extension of the fourth frame; and the output terminal part which is provided on an extension to which the second frame and the third frame are electrically joined, wherein the third frame and the fourth frame are arranged in parallel with each other, and the electric source terminal part, the ground terminal part and the output terminal part are arranged in a manner such that induced electric voltages, which are generated in the third frame and the fourth frame, become in reverse directions with each other.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: December 13, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Kenya Yamashita
  • Publication number: 20160046839
    Abstract: Provided is a removable self-adhesive film excellent in stylus-friendliness and the adhesiveness between an adhesive layer and a substrate layer. The removable self-adhesive film includes a substrate layer, an adhesive layer, and a primer layer between the substrate layer and the adhesive layer, in which the adhesive layer comprises a vinyl group-containing thermoplastic elastomer, an acrylic acid ester, a photopolymerization initiator, and a plasticizer, and the primer layer is composed of a polymer that comprises a polyester-based polymer as a main component and has a hydroxyl group or a vinyl group.
    Type: Application
    Filed: August 14, 2014
    Publication date: February 18, 2016
    Inventors: Masanori MARUNO, Kenya YAMASHITA, Kazuo MACHIDA, Motoki SHIGETO, Yuichiro KUBOTA
  • Publication number: 20150115423
    Abstract: Included are: the third frame which is electrically connected to the first intermediate frame and is arranged above the first frame; the fourth frame which is electrically connected to the second intermediate frame and is arranged above the second frame; the electric source terminal part which is provided on an extension of the first frame; the ground terminal part which is provided on an extension of the fourth frame; and the output terminal part which is provided on an extension to which the second frame and the third frame are electrically joined, wherein the third frame and the fourth frame are arranged in parallel with each other, and the electric source terminal part, the ground terminal part and the output terminal part are arranged in a manner such that induced electric voltages, which are generated in the third frame and the fourth frame, become in reverse directions with each other.
    Type: Application
    Filed: May 7, 2013
    Publication date: April 30, 2015
    Inventor: Kenya Yamashita
  • Publication number: 20150008443
    Abstract: A semiconductor device includes a semiconductor module including a high-side first transistor and a low-side second transistor, a first control board located above the semiconductor module, a drive element connected to a first gate terminal and a first source terminal of the first transistor on the first control board, and a drive element connected to a second gate terminal and a second source terminal of the second transistor on the first control board, a second control board located above the first control board, and photocouplers provided on the second control board. The semiconductor module includes a positive electrode terminal, a ground terminal, and an output terminal. The first gate terminal and the first source terminal are located at the side provided with the positive electrode terminal and the ground terminal. The second gate terminal and the second source terminal are located at the side provided with the output terminal.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 8, 2015
    Inventor: Kenya YAMASHITA
  • Patent number: 8916967
    Abstract: A semiconductor device includes a semiconductor module including a high-side first transistor and a low-side second transistor, a first control board located above the semiconductor module, a drive element connected to a first gate terminal and a first source terminal of the first transistor on the first control board, and a drive element connected to a second gate terminal and a second source terminal of the second transistor on the first control board, a second control board located above the first control board, and photocouplers provided on the second control board. The semiconductor module includes a positive electrode terminal, a ground terminal, and an output terminal. The first gate terminal and the first source terminal are located at the side provided with the positive electrode terminal and the ground terminal. The second gate terminal and the second source terminal are located at the side provided with the output terminal.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: December 23, 2014
    Assignee: Panasonic Corporation
    Inventor: Kenya Yamashita
  • Patent number: 8754422
    Abstract: A semiconductor device 100 includes: a first silicon carbide layer 120 arranged on the principal surface of a semiconductor substrate 101; a first impurity region 103 of a first conductivity type arranged in the first silicon carbide layer; a body region 104 of a second conductivity type; a contact region 131 of the second conductivity type which is arranged at a position in the body region that is deeper than the first impurity region 103 and which contains an impurity of the second conductivity type at a higher concentration than the body region; a drift region 102 of the first conductivity type; and a first ohmic electrode 122 in ohmic contact with the first impurity region 103 and the contact region 131, wherein: a contact trench 121, which penetrates through the first impurity region 103, is provided in the first silicon carbide layer 120; and the first ohmic electrode 122 is arranged in the contact trench 121 and is in contact with the contact region 131 on at least a portion of a side wall lower portio
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: June 17, 2014
    Assignee: Panasonic Corporation
    Inventors: Chiaki Kudou, Kenya Yamashita, Masahiko Niwayama
  • Patent number: 8703382
    Abstract: A photosensitive resin composition for flexographic printing having excellent resistance to an ink comprising an organic solvent and an emulsion ink used in flexographic printing, for example, a UV-curable ink or an ink using a vegetable oil or light naphtha and having excellent suitability for printing applications such as image reproducibility and print durability. The photosensitive resin composition for flexographic printing includes, at least, (a) one or more thermoplastic elastomers, (b) an acrylic-terminated liquid polybutadiene containing 1,2-bonds in an amount of 80% or more, (c) a photopolymerizable unsaturated monomer having at least one or more ethylenically unsaturated groups, and (d) a photopolymerization initiator.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: April 22, 2014
    Assignee: Nippon Soda Co., Ltd.
    Inventors: Masanori Maruno, Jun Yoshida, Kenya Yamashita, Yukikazu Nobuhara
  • Patent number: 8699228
    Abstract: A reliable power module is realized, in which a good performance of radiating heat of the power semiconductor element is secured and it is hard for the heat of a power semiconductor element to be conducted to a driving element. A power module includes a power semiconductor element mounted on a lead frame, and a driving element mounted on the lead frame, and a heat radiating plate radiating heat which is generated by the power semiconductor element, and a resin holding the power semiconductor element, the driving element, and the heat radiating plate, wherein the heat radiating plate has a portion disposed at a side opposite to a surface of the lead frame where the power semiconductor element is mounted, a portion disposed between the power semiconductor element and the driving element, and a portion disposed below the power semiconductor element, as the portions being in a body.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: April 15, 2014
    Assignee: Panasonic Corporation
    Inventors: Keiko Takahashi, Masanori Minamio, Kenya Yamashita
  • Patent number: 8530943
    Abstract: The semiconductor device includes: a substrate 2 and a drift layer 3a, which are made of a wide-bandgap semiconductor; a p-type well 4a and a first n-type doped region 5, which are defined in the drift layer; a source electrode 5, which is electrically connected to the first n-type doped region 5; a second n-type doped region 30 arranged between its own well 4a and an adjacent unit cell's well 4a; a gate insulating film 7b, which covers at least partially the first and second n-type doped regions and the well 4a; a gate electrode 8 arranged on the gate insulating film; and a third n-type doped region 31, which is arranged adjacent to the second n-type doped region so as to cover one of the vertices of the unit cell and which has a dopant concentration that is higher than the drift layer and lower than the second n-type doped region.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: September 10, 2013
    Assignee: Panasonic Corporation
    Inventors: Kenya Yamashita, Chiaki Kudou
  • Patent number: 8421151
    Abstract: The semiconductor device of this invention has unit cells, each of which includes: a substrate; a drift layer on the substrate; a body region in the drift layer; a first doped region of a first conductivity type in the body region; a second doped region of the first conductivity type arranged adjacent to the body region and in a surface region of the drift layer; a third doped region of the first conductivity type arranged between two adjacent unit cells' second doped region of the first conductivity type and in the surface region of the drift layer to contact with the second doped region of the first conductivity type; a gate insulating film arranged to contact with the surface of the drift layer at least between the first and second doped regions of the first conductivity type; a gate electrode on the gate insulating film; and first and second ohmic electrodes.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: April 16, 2013
    Assignee: Panasonic Corporation
    Inventor: Kenya Yamashita
  • Publication number: 20120218717
    Abstract: A reliable power module is realized, in which a good performance of radiating heat of the power semiconductor element is secured and it is hard for the heat of a power semiconductor element to be conducted to a driving element. A power module includes a power semiconductor element mounted on a lead frame, and a driving element mounted on the lead frame, and a heat radiating plate radiating heat which is generated by the power semiconductor element, and a resin holding the power semiconductor element, the driving element, and the heat radiating plate, wherein the heat radiating plate has a portion disposed at a side opposite to a surface of the lead frame where the power semiconductor element is mounted, a portion disposed between the power semiconductor element and the driving element, and a portion disposed below the power semiconductor element, as the portions being in a body.
    Type: Application
    Filed: February 23, 2012
    Publication date: August 30, 2012
    Applicant: Panasonic Corporation
    Inventors: Keiko TAKAHASHI, Masanori Minamio, Kenya Yamashita
  • Publication number: 20120205670
    Abstract: A semiconductor device 100 includes: a first silicon carbide layer 120 arranged on the principal surface of a semiconductor substrate 101; a first impurity region 103 of a first conductivity type arranged in the first silicon carbide layer; a body region 104 of a second conductivity type; a contact region 131 of the second conductivity type which is arranged at a position in the body region that is deeper than the first impurity region 103 and which contains an impurity of the second conductivity type at a higher concentration than the body region; a drift region 102 of the first conductivity type; and a first ohmic electrode 122 in ohmic contact with the first impurity region 103 and the contact region 131, wherein: a contact trench 121, which penetrates through the first impurity region 103, is provided in the first silicon carbide layer 120; and the first ohmic electrode 122 is arranged in the contact trench 121 and is in contact with the contact region 131 on at least a portion of a side wall lower portio
    Type: Application
    Filed: October 19, 2010
    Publication date: August 16, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Chiaki Kudou, Kenya Yamashita, Masahiko Niwayama
  • Publication number: 20120205739
    Abstract: The semiconductor device of this invention has unit cells, each of which includes: a substrate; a drift layer on the substrate; a body region in the drift layer; a first doped region of a first conductivity type in the body region; a second doped region of the first conductivity type arranged adjacent to the body region and in a surface region of the drift layer; a third doped region of the first conductivity type arranged between two adjacent unit cells' second doped region of the first conductivity type and in the surface region of the drift layer to contact with the second doped region of the first conductivity type; a gate insulating film arranged to contact with the surface of the drift layer at least between the first and second doped regions of the first conductivity type; a gate electrode on the gate insulating film; and first and second ohmic electrodes.
    Type: Application
    Filed: October 19, 2010
    Publication date: August 16, 2012
    Applicant: PANASONIC CORPORATION
    Inventor: Kenya Yamashita