Abstract: In a semiconductor device of the present invention, the top surface of an n-type silicon carbide layer formed on a silicon carbide substrate is miscut from the (0001) plane in the <11-20> direction. A gate electrode, a source electrode and other elements are arranged such that in a channel region, the dominating current flows along a miscut direction. In the present invention, a gate insulating film is formed and then heat treatment is performed in an atmosphere containing a group-V element. In this way, the interface state density at the interface between the silicon carbide layer and the gate insulating film is reduced. As a result, the electron mobility becomes higher in a miscut direction A than in the direction perpendicular to the miscut direction A.

Abstract: A semiconductor device according to this invention includes: two level shift switches (28A and 28B) each having first and second electrodes, a control electrode, a signal output electrode, and a first semiconductor region forming a transistor device section (28a,28b) which intervenes between the first electrode and the signal output electrode and is brought into or out of conduction according to a signal inputted to the control electrode and a resistor device section (Ra,Rb) which intervenes between the signal output electrode and the second electrode, the first semiconductor region comprising a wide bandgap semiconductor; and a diode (23) having a cathode-side electrode, an anode-side electrode, and a second semiconductor region comprising a wide bandgap semiconductor.

Abstract: A semiconductor module comprises independently operable segments 1 (semiconductor elements) on a SiC substrate. Each segment 1 comprises a source electrode pad 2 and a gate electrode pad 3 both provided to the principal surface side of the SiC substrate, and a drain electrode pad provided on the back surface side of the SiC substrate. The semiconductor module further comprises an isolation region such as a trench or a Schottky diode for electrically isolating the adjacent segments 1 from each other. Only electrode pads 2 and 3 of each of the segments 1 determined as conforming items by a test are connected to electrode terminals 41 and 43, respectively.

Abstract: An inventive semiconductor device is provided with: a silicon carbide substrate 1; an n-type high resistance layer 2; well regions 3 provided in a surface region of the high resistance layer 2; a p+ contact region 4 provided within each well region 3; a source region 5 provided to laterally surround the p+ contact region 4 within each well region 3; first source electrodes 8 provided on the source regions 5 and made of nickel; second source electrodes 9 that cover the first source electrodes 8 and that are made of aluminum; a gate insulating film 6 provided on a portion of the high resistance layer 2 sandwiched between the two well regions 3; a gate electrode 10 made of aluminum; and an interlayer dielectric film 11 that covers the second source electrodes 9 and the gate electrode 10 and that is made of silicon oxide.

Abstract: In a semiconductor device of the present invention, the top surface of an n-type silicon carbide layer formed on a silicon carbide substrate is miscut from the (0001) plane in the <11-20> direction. A gate electrode, a source electrode and other elements are arranged such that in a channel region, the dominating current flows along a miscut direction. In the present invention, a gate insulating film is formed and then heat treatment is performed in an atmosphere containing a group-V element. In this way, the interface state density at the interface between the silicon carbide layer and the gate insulating film is reduced. As a result, the electron mobility becomes higher in a miscut direction A than in the direction perpendicular to the miscut direction A.

Abstract: A method for fabricating a semiconductor device includes the steps of implanting ions into a silicon carbide thin film (2) formed on a silicon carbide substrate (1), heating the silicon carbide substrate in a reduced pressure atmosphere to form a carbon layer (5) on the surface of the silicon carbide substrate, and performing activation annealing with respect to the silicon carbide substrate in an atmosphere under a pressure higher than in the step of forming the carbon layer (5) and at a temperature higher than in the step of forming the carbon layer (5).

Abstract: In a semiconductor device of the present invention, the top surface of an n-type silicon carbide layer formed on a silicon carbide substrate is miscut from the (0001) plane in the <11-20> direction. A gate electrode, a source electrode and other elements are arranged such that in a channel region, the dominating current flows along a miscut direction. In the present invention, a gate insulating film is formed and then heat treatment is performed in an atmosphere containing a group-V element. In this way, the interface state density at the interface between the silicon carbide layer and the gate insulating film is reduced. As a result, the electron mobility becomes higher in a miscut direction A than in the direction perpendicular to the miscut direction A.

Abstract: A semiconductor apparatus includes a semiconductor chip 61 including a power semiconductor device using a wide band gap semiconductor, base materials 62 and 63, first and second intermediate members 65 and 68a, a heat conducting member 66, a radiation fin 67, and an encapsulating material 68 for encapsulating the semiconductor chip 61, the first and second intermediate member 65 and 68a and the heat conducting member 66. The tips of the base materials 62 and 63 work respectively as external connection terminals 62a and 63a. The second intermediate member 68a is made of a material with lower heat conductivity than the first intermediate member 65, and a contact area with the semiconductor chip 61 is larger in the second intermediate member 68a than in the first intermediate member.

Abstract: A semiconductor device having an accumulation channel SiC-MISFET structure includes a p-type SiC layer 10 formed on an SiC substrate, an n-type channel layer 20, a gate insulating film 11, a gate electrode 12, and n-type source and drain layers 13a and 13b. The channel layer 20 includes an undoped layer 22 and a ? doped layer 21 which is formed in the vicinity of the lower end of the undoped layer 22. Since the channel layer 20 includes the high-concentration ? doped layer 21 in its deeper portion, the electric field in the surface region of the channel layer is weakened, thereby allowing the current driving force to increase.

Abstract: A SiC bulk substrate whose top face has been flattened is placed in a vertical thin film growth system to be annealed in an inert gas atmosphere. A material gas of Si is then supplied at a flow rate of 1 mL/min. at a substrate temperature of 1200° C. through 1600° C. Subsequently, the diluent gas is changed to a hydrogen gas at a temperature of 1600° C., and material gases of Si and carbon are supplied with nitrogen intermittently supplied, so as to deposit SiC thin films on the SiC bulk substrate. In a flat ?-doped multilayered structure thus formed, an average height of macro steps formed on the top face and on interfaces therein is 30 nm or less. When the resultant substrate is used, a semiconductor device with a high breakdown voltage and high mobility can be realized.

Abstract: A storage-type SiC-MISFET includes a SiC substrate, an n-type drift layer, a p-type well region, an n-type source region, a SiC channel layer which contains an n-type impurity and is to be a storage-type channel layer, a p-type heavily doped contact layer, a gate insulation film, a gate electrode and the like. In the storage-type SiC-MISFET, a partially heavily doped layer is formed by partially implanting ions of a p-type impurity into an upper surface portion of the n-type drift layer and containing an impurity of the same conductive type as that of the impurity implanted into the well region at a higher concentration than that in the well region.

Abstract: An accumulation-mode MISFET comprises: a high-resistance SiC layer 102 epitaxially grown on a SiC substrate 101; a well region 103; an accumulation channel layer 104 having a multiple ?-doped layer formed on the surface region of the well region 103; a contact region 105; a gate insulating film 108; and a gate electrode 110. The accumulation channel layer 104 has a structure in which undoped layers 104b and ?-doped layers 104a allowing spreading movement of carriers to the undoped layers 104b under a quantum effect are alternately stacked. A source electrode 111 is provided which enters into the accumulation channel layer 104 and the contact region 105 to come into direct contact with the contact region 105. It becomes unnecessary that a source region is formed by ion implantation, leading to reduction in fabrication cost.

Abstract: A Schottky diode includes a semiconductor substrate made of 4H—SiC, an epitaxially grown 4H—SiC layer, an ion implantation layer, a Schottky electrode, an ohmic electrode, and an insulative layer made of a thermal oxide film. The Schottky electrode and the insulative layer are not in contact with each other, with a gap being provided therebetween, whereby an altered layer does not occur. Therefore, it is possible to suppress the occurrence of a leak current.

Abstract: A gate insulating film which is an oxide layer mainly made of SiO2 is formed over a silicon carbide substrate by thermal oxidation, and then, a resultant structure is annealed in an inert gas atmosphere in a chamber. Thereafter, the silicon carbide-oxide layered structure is placed in a chamber which has a vacuum pump and exposed to a reduced pressure NO gas atmosphere at a high temperature higher than 1100° C. and lower than 1250° C., whereby nitrogen is diffused in the gate insulating film. As a result, a gate insulating film which is a V-group element containing oxide layer, the lower part of which includes a high nitrogen concentration region, and the relative dielectric constant of which is 3.0 or higher, is obtained. The interface state density of an interface region between the V-group element containing oxide layer and the silicon carbide layer decreases.

Abstract: An upper part of a SIC substrate 1 is oxidized at a temperature of 800 to 1400° C., inclusive, in an oxygen atmosphere at 1.4×102 Pa or less, thereby forming a first insulating film 2 which is a thermal oxide film of 20 nm or less in thickness. Thereafter, annealing is performed, and then a first cap layer 3, which is a nitride film of about 5 nm in thickness, is formed thereon by CVD. A second insulating film 4, which is an oxide film of about 130 nm in thickness, is deposited thereon by CVD. A second cap layer 5, which is a nitride film of about 10 nm in thickness, is formed thereon. In this manner, a gate insulating film 6 made of the first insulating film 2 through the second cap layer 5 is formed, thus obtaining a low-loss highly-reliable semiconductor device.

Abstract: Ion implantation is carried out to form a p-well region and a source region in parts of a high resistance SiC layer on a SiC substrate, and a carbon film is deposited over the substrate. With the carbon film deposited over the substrate, annealing for activating the implanted dopant ions is performed, and then the carbon film is removed. Thus, a smooth surface having hardly any surface roughness caused by the annealing is obtained. Furthermore, if a channel layer is epitaxially grown, the surface roughness of the channel layer is smaller than that of the underlying layer. Since the channel layer having a smooth surface is provided, it is possible to obtain a MISFET with a high current drive capability.

Abstract: A semiconductor module comprises independently operable segments 1 (semiconductor elements) on a SiC substrate. Each segment 1 comprises a source electrode pad 2 and a gate electrode pad 3 both provided to the principal surface side of the SiC substrate, and a drain electrode pad provided on the back surface side of the SiC substrate. The semiconductor module further comprises an isolation region such as a trench or a Schottky diode for electrically isolating the adjacent segments 1 from each other. Only electrode pads 2 and 3 of each of the segments 1 determined as conforming items by a test are connected to electrode terminals 41 and 43, respectively.

Abstract: An inventive semiconductor device is provided with: a silicon carbide substrate 1; an n-type high resistance layer 2; well regions 3 provided in a surface region of the high resistance layer 2; a p+ contact region 4 provided within each well region 3; a source region 5 provided to laterally surround the p+ contact region 4 within each well region 3; first source electrodes 8 provided on the source regions 5 and made of nickel; second source electrodes 9 that cover the first source electrodes 8 and that are made of aluminum; a gate insulating film 6 provided on a portion of the high resistance layer 2 sandwiched between the two well regions 3; a gate electrode 10 made of aluminum; and an interlayer dielectric film 11 that covers the second source electrodes 9 and the gate electrode 10 and that is made of silicon oxide.

Abstract: An image displaying device 13 comprising a display unit for displaying images produced when a three-dimensional model is viewed from a predetermined observing point, and an input means provided along the display surface of the display unit, characterized in that the display unit is constituted by a plasma display device and can control images by operating the input means. An image processing device which displays on a display means images produced when a plurality of moving bodies (such as fish) moving in a virtual three-dimensional space are viewed from a predetermined observing point, and which determines the above observing point position based on a status of one or a group of moving bodies moving together uniformly selected from among the plurality of moving bodies, thereby providing a high-playing-level playing device in a viewing amusement device or the like which produces viewing images indicating the behaviors of a plurality of moving bodies.

Abstract: A storage-type SiC-MISFET includes a SiC substrate, an n-type drift layer, a p-type well region, an n-type source region, a SiC channel layer which contains an n-type impurity and is to be a storage-type channel layer, a p-type heavily doped contact layer, a gate insulation film, a gate electrode and the like. In the storage-type SiC-MISFET, a partially heavily doped layer is formed by partially implanting ions of a p-type impurity into an upper surface portion of the n-type drift layer and containing an impurity of the same conductive type as that of the impurity implanted into the well region at a higher concentration than that in the well region.