Patents by Inventor Kenzo Hatada
Kenzo Hatada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6953991Abstract: A semiconductor device comprising a laminate of plural insulating substrates 101 to 104 on which are mounted semiconductor chips (electronic parts) 12, wherein, when the lower-most insulating substrate is regarded to be a first insulating substrate 101 and other insulating substrates to be second insulating substrates 102 to 104 among the insulating substrates that are laminated; second electrically conducting wirings 112 to 114 are so provided as to protrude beyond the peripheral edges of the second insulating substrates and are folded toward the side of other surfaces of the second insulating substrates, and the thus folded second electrically conducting wirings are electrically connected to the electrically conducting wirings on the lower insulating substrates.Type: GrantFiled: June 1, 2001Date of Patent: October 11, 2005Assignee: Shindo Company, Ltd.Inventors: Kenzo Hatada, Kozo Sato
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Patent number: 6917143Abstract: A lighting apparatus comprises an LED-mounted substrate and an exhauster. The substrate has a flat area as well as one or more raised areas of trapezoidal cross section which each form a passage thereunder. LEDs are mounted on the raised areas. When the LED-mounted substrate is installed on a wall, the passages are enclosed by the wall. The exhauster removes the heat from the LEDs by drawing out the air going through inside the passages.Type: GrantFiled: September 13, 2002Date of Patent: July 12, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Nobuyuki Matsui, Hideo Nagai, Tetsushi Tamura, Kenzo Hatada
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Patent number: 6883933Abstract: In the present invention, a plurality of concaves are provided for one main surface of a flexible substrate by press-forming. Each concave has a flat surface which is substantially parallel to the main surface of the substrate, and mounted on the flat surface are three LEDs each emitting colored light of red, green, and blue respectively.Type: GrantFiled: September 17, 2002Date of Patent: April 26, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Nobuyuki Matsui, Hideo Nagai, Tetsushi Tamura, Kenzo Hatada
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Publication number: 20040251536Abstract: A semiconductor device comprising a laminate of plural insulating substrates 101 to 104 on which are mounted semiconductor chips (electronic parts) 12, wherein, when the lower-most insulating substrate is regarded to be a first insulating substrate 101 and other insulating substrates to be second insulating substrates 102 to 104 among the insulating substrates that are laminated;Type: ApplicationFiled: January 13, 2003Publication date: December 16, 2004Inventors: Kenzo Hatada, Kozo Sato
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Publication number: 20030052594Abstract: In the present invention, a plurality of concaves are provided for one main surface of a flexible substrate by press-forming. Each concave has a flat surface which is substantially parallel to the main surface of the substrate, and mounted on the flat surface are three LEDs each emitting colored light of red, green, and blue respectively.Type: ApplicationFiled: September 17, 2002Publication date: March 20, 2003Inventors: Nobuyuki Matsui, Hideo Nagai, Tetsushi Tamura, Kenzo Hatada
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Publication number: 20030052584Abstract: A lighting apparatus comprises an LED-mounted substrate and an exhauster. The substrate has a flat area as well as one or more raised areas of trapezoidal cross section which each form a passage thereunder. LEDs are mounted on the raised areas. When the LED-mounted substrate is installed on a wall, the passages are enclosed by the wall. The exhauster removes the heat from the LEDs by drawing out the air going through inside the passages.Type: ApplicationFiled: September 13, 2002Publication date: March 20, 2003Inventors: Nobuyuki Matsui, Hideo Nagai, Tetsushi Tamura, Kenzo Hatada
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Patent number: 6492255Abstract: A via 42 is formed by copper plating on a surface of an aluminum electrode pad 32 of a semiconductor chip 30. Since the via 42 having flexibility absorbs a stress generated due to a difference in thermal expansion between the semiconductor chip 30 and a substrate, the semiconductor chip 30 can be mounted onto the substrate 50 with high reliability and connection reliability of the semiconductor chip 30 can be enhanced.Type: GrantFiled: March 30, 2001Date of Patent: December 10, 2002Assignee: Ibiden Co., LTDInventors: Ryo Enomoto, Hideo Yabashi, Tadashi Sugiyama, Kenzo Hatada
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Publication number: 20010049187Abstract: A via 42 is formed by copper plating on a surface of an aluminum electrode pad 32 of a semiconductor chip 30. Since the via 42 having flexibility absorbs a stress generated due to a difference in thermal expansion between the semiconductor chip 30 and a substrate, the semiconductor chip 30 can be mounted onto the substrate 50 with high reliability and connection reliability of the semiconductor chip 30 can be enhanced.Type: ApplicationFiled: March 30, 2001Publication date: December 6, 2001Applicant: IBIDEN, CO., LTD.Inventors: Ryo Enomoto, Hideo Yabashi, Tadashi Sugiyama, Kenzo Hatada
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Patent number: 5998866Abstract: A plurality of connecting leads, each consisting of an internal lead and an external lead, are provided so as to extend inward from a lead frame main body, and are then cut off the lead frame main body. The connecting leads are electrically connected with an aluminum electrode of the semiconductor chip. A plurality of fixing leads, each having a distal end bent toward the semiconductor, are provided so as to extend inward from the lead frame main body and thereafter are cut off the lead frame main body. The semiconductor chip is clamped by the distal ends of the fixing leads. The semiconductor chip, the plural connecting leads and the plural fixing leads are sealed together into a resin package.Type: GrantFiled: January 16, 1998Date of Patent: December 7, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takao Ochi, Hisashi Funakoshi, Kenzo Hatada, Takashi Wakabayashi
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Patent number: 5796714Abstract: The optical module of the invention includes: a first substrate; a vertical-cavity surface-emitting laser including an upper surface, a bottom surface and a semiconductor multi-layered structure including at least a light-emitting layer, the vertical-cavity surface-emitting laser being supported on the first substrate; an electrode structure electrically connected with the bottom surface of the vertical-cavity surface-emitting laser, the electrode structure being supported on the first substrate; and a second substrate including a first bump and a second bump. In the optical module, an upper surface of the electrode structure and the upper surface of the vertical-cavity surface-emitting laser jut out from the first substrate. The second substrate is positioned with respect to the first substrate so that the first bump and the second bump come into contact with an upper surface of the electrode structure and the upper surface of the vertical-cavity surface-emitting laser, respectively.Type: GrantFiled: September 25, 1995Date of Patent: August 18, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toyoji Chino, Kenichi Matsuda, Takayuki Yoshida, Kenzo Hatada
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Patent number: 5783463Abstract: The present invention is premised on a semiconductor device in which one semiconductor chip is mounted on each of both faces of a die pad of a lead frame. The semiconductor chips are disposed such that the projected lines, on the die pad, of the corresponding sides of the semiconductor chips, intersect with each other at an angle of 45.degree.. The tips of inner leads are located in the sides of a virtual octagon formed by outwardly enlarging an octagon formed by connecting, to one another, the apexes of the semiconductor chips. The sides of the virtual octagon are respectively opposite to the sides of the semiconductor chips. The number of the inner leads of which tips are located in each of the sides of the virtual octagon, is the same as the number of bonding pads disposed at each of the sides of the semiconductor chips.Type: GrantFiled: February 4, 1997Date of Patent: July 21, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shinitsu Takehashi, Kenzo Hatada
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Patent number: 5776802Abstract: A plurality of connecting leads, each consisting of an internal lead and an external lead, are provided so as to extend inward from a lead frame main body, and are then cut off the lead frame main body. The connecting leads are electrically connected with an aluminum electrode of the semiconductor chip. A plurality of fixing leads, each having a distal end bent toward the semiconductor, are provided so as to extend inward from the lead frame main body and thereafter are cut off the lead frame main body. The semiconductor chip is clamped by the distal ends of the fixing leads. The semiconductor chip, the plural connecting leads and the plural fixing leads are sealed together into a resin package.Type: GrantFiled: October 31, 1996Date of Patent: July 7, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takao Ochi, Hisashi Funakoshi, Kenzo Hatada, Takashi Wakabayashi
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Process for bonding a semiconductor to a circuit substrate including a solder bump transferring step
Patent number: 5739053Abstract: A process wherein substrate preliminary formed with bumps by electrolytic plating or other technique is prepared. The semiconductor device is opposed to the substrate with the bumps so that the Al electrodes of the semiconductor device are aligned with respect to the bumps and brought into contact with each other. Then, the Al electrodes of the semiconductor device and the bumps are bonded together by the application of pressure and heat with an Au--Al alloy layer formed therebetween. Subsequently, the bumps are peeled off the substrate so as to be transferred to the respective Al electrodes. Thereafter, the semiconductor device is opposed to a circuit board so that the bumps are aligned with respect to the electrodes of wiring and brought into contact with them.Type: GrantFiled: May 15, 1995Date of Patent: April 14, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tetuo Kawakita, Kenzo Hatada -
Patent number: 5665610Abstract: A plated layer made of a metal which is hard to oxidize is formed on the surface of a check electrode of a semiconductor chip which is formed on a semiconductor wafer. A bump of a contactor is caused to come in contact with the check electrode on which the plated layer is formed in the direction perpendicular to the semiconductor chip. Then, a voltage is applied to the bump of the contactor to make a check such as burn-in on the semiconductor chip in a lump.Type: GrantFiled: May 17, 1996Date of Patent: September 9, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshiro Nakata, Shinichi Oki, Koichi Nagao, Kenzo Hatada, Shigeoki Mori, Takashi Sato, Kunio Sano
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Patent number: 5640044Abstract: The present invention is premised on a semiconductor device in which one semiconductor chip is mounted on each of both faces of a die pad of a lead frame. The semiconductor chips are disposed such that the projected lines, on the die pad, of the corresponding sides of the semiconductor chips, intersect with each other at an angle of 45.degree.. The tips of inner leads are located in the sides of a virtual octagon formed by outwardly enlarging an octagon formed by connecting, to one another, the apexes of the semiconductor chips. The sides of the virtual octagon are respectively opposite to the sides of the semiconductor chips. The number of the inner leads of which tips are located in each of the sides of the virtual octagon, is the same as the number of bonding pads disposed at each of the sides of the semiconductor chips.Type: GrantFiled: April 13, 1995Date of Patent: June 17, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shinitsu Takehashi, Kenzo Hatada
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Patent number: 5477087Abstract: The present invention relates to connecting electronic components using bump electrodes to connect electronic components such as semiconductors with the patterning electrodes of a circuit board. In order to prevent deterioration in connecting reliability due to deformation and the like of semiconductors and circuit boards, it is necessary to have some elasticity incorporated within bump electrodes. The bump electrodes disclosed by the present invention have resin bumps with numerous cavities disposed within and covered by a low melting point metal layer. According to this composition, even when there are some variations of distribution in circuit board warp and bump electrode height, it is possible to absorb the variations through the elasticity presented by the bump electrodes. It is also possible to perform a low strain connection with a resultant enhancement in connecting reliability at high temperature.Type: GrantFiled: November 18, 1994Date of Patent: December 19, 1995Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tetsuo Kawakita, Kenzo Hatada
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Patent number: 5336547Abstract: The present invention relates to an electronic components mounting/connecting package characterized by using bump electrodes to connect electronic components such as semiconductors and the like with patterning electrodes of a circuit board.In order to prevent deterioration in connecting reliability due to deformation and the like of semiconductors and circuit boards, it is necessary to have some elasticity incorporated with bump electrodes. The composition of bump electrodes disclosed by the present invention is to have resin particles dispersed to high density in the metallic bump electrodes.According to this composition, even when there are some variations of distribution in circuit board warp and bump electrode height, it has become possible to absorb the variations through elasticity presented by the bump electrodes and to perform a low strain connection with a resultant enhancement in connecting reliability at high temperature.Type: GrantFiled: February 26, 1993Date of Patent: August 9, 1994Assignee: Matsushita Electric Industrial Co. Ltd.Inventors: Tetsuo Kawakita, Takayuki Yoshida, Kenzo Hatada
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Patent number: 5316610Abstract: A depression jig, having a depression chip and a holder for holding the depression chip, is provided which depresses against a wiring substrate a semiconductor chip placed on the wiring substrate. The holder has portions defining penetrations vertically running through the holder. Optical fibers are inserted into the penetrations. A light ray radiates from the optical fiber. The light ray is incident upon the top surface of the depression chip, enters the depression chip, is reflected from a side surface of the depression chip onto the undersurface of the depression chip, and is emitted from the undersurface of the depression chip as an outgoing light ray. A photo-curing resin supplied between the semiconductor chip and the wiring substrate is irradiated with such an outgoing light ray, so that the photo-curing resin hardens.Type: GrantFiled: December 18, 1992Date of Patent: May 31, 1994Assignees: Matsushita Electric Industrial Co., Ltd., Matsushita Electronics CorporationInventors: Tomohiro Tamaki, Kenzo Hatada, Hiroaki Fujimoto, Yoshinobu Takeshita
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Patent number: 5316204Abstract: A method for bonding leads of a film carrier to electrodes of electronic devices includes a step for positioning the leads and the electrodes with a predetermined clearance aligned to define corresponding pairs of the leads and electrodes, and a step for placing a bonding tool having a conductive bonding material served such that the conductive bonding material is located between the lead and electrode of one of the corresponding pairs. The method further includes a step for pressing the lead of one corresponding pair such that the conductive bonding material is pressed between the lead and the electrode, thereby bonding the lead and electrode. After bonding, the conductive bonding material is pulled to cut and leave the bonded conductive bonding material. Then, while the bonding tool is released from the bonded pair, the conductive bonding material is served to the bonding tool for the next bonding operation.Type: GrantFiled: November 9, 1992Date of Patent: May 31, 1994Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shinitsu Takehashi, Kenzo Hatada, Hiroaki Fujimoto
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Patent number: 5233426Abstract: The present invention provides a compact camera head for a solid-state image pickup device, a dimension of which is not so limited by a package for a solid-state image pickup element. Outer-leads are connected via inner-leads respectively to electrodes of a solid-state image pickup chip to constitute the solid-state image pickup element. An optical glass plate is attached to a light-receiving surface of the solid-state image pickup chip. The outer-leads are connected to side electrodes of a circuit module constituted by a chip-connecting board, a circuit board and a connector board, to thereby provide an image pickup unit. The image pickup unit is inserted into a chassis, and the opposite open ends of the chassis are sealed by an optical filter and a seal plate.Type: GrantFiled: December 12, 1991Date of Patent: August 3, 1993Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takahisa Suzuki, Tatsuki Tsukada, Kenzo Hatada