Abstract: A computing apparatus that does not need quantum coherence or a cryogenic cooling apparatus is provided for assignments that need an exhaustive search. A system is led to the ground state of the system where a problem is set, wherein spin sjz that is a variable follows a local effective magnetic field Bjz. The spin state at t=0 is initialized with a transverse field (in the x-direction). This corresponds to sjz=0. With time t, the magnetic field in the z-axis direction and the inter-spin interactions are gradually added, and finally the spin is directed to the +z- or ?z-direction. The z component of the spin sj is sjz=+1 or ?1. Here, in the process where the orientation of the spin sjz follows that of the effective magnetic field Bjz, correction parameters originating in quantum-mechanical effects are introduced and ground-state-maintaining performance is improved.

Abstract: A computer includes a data generation unit and a storage unit which retains graph information for managing a graph configured from a plurality of vertexes and sides. The data generation unit performs acquiring a plurality of data and graph information and assuring storage regions in number equal to the number of vertexes, converting each data into an input value and setting at least one input value to a storage region corresponding to at least one vertex, executing an updating process for updating a value set to a storage region corresponding to a first vertex using the value set to the storage region corresponding to the first vertex and a value set to a storage region corresponding to a different vertex directly connected to the first vertex, and outputting a set of values set to the storage regions corresponding to the vertexes as the feature value.

Abstract: An object of the present invention is to provide an artificial olfactory sensing system capable of sniffing out various odors highly sensitively. The artificial olfactory sensing system includes: plural sensor cells on a lipid membrane of each of which olfactory receptors have developed; and plural ion-sensitive field-effect transistors (ISFETs) that correspondingly exist to the sensor cells on a one-on-one basis. A response signal showing that each of the olfactory receptors of each of the sensor cells has recognized an odor molecule is converted into an electric signal by an ISFET corresponding to each of the sensor cells.

Abstract: A computing apparatus that does not need quantum coherence or a cryogenic cooling apparatus is provided for assignments that need an exhaustive search. A system is led to the ground state of the system where a problem is set, wherein spin sjz that is a variable follows a local effective magnetic field Bjz. The spin state at t=0 is initialized with a transverse field (in the x-direction). This corresponds to sjz=0. With time t, the magnetic field in the z-axis direction and the inter-spin interactions are gradually added, and finally the spin is directed to the +z- or ?z-direction. The z component of the spin sj is sjz=+1 or ?1. Here, in the process where the orientation of the spin sjz follows that of the effective magnetic field Bjz, correction parameters originating in quantum-mechanical effects are introduced and ground-state-maintaining performance is improved.

Abstract: An object of the present invention is to provide an artificial olfactory sensing system capable of sniffing out various odors highly sensitively. The artificial olfactory sensing system includes: plural sensor cells on a lipid membrane of each of which olfactory receptors have developed; and plural ion-sensitive field-effect transistors (ISFETs) that correspondingly exist to the sensor cells on a one-on-one basis. A response signal showing that each of the olfactory receptors of each of the sensor cells has recognized an odor molecule is converted into an electric signal by an ISFET corresponding to each of the sensor cells.

Abstract: Information appropriate for supporting various judgments in organization activities is provided. A judgment support system for supporting a user's judgment, includes: a processor that executes a program; a storage section that can be accessed by the processor; and an output section that outputs data for displaying an execution result of the program. The judgment support system further includes: an extraction section that searches a predetermined sentence expression from data stored in the storage section, and extracts an issue of an organization using text having a predetermined relationship with the searched sentence expression; and a first selection section that selects a second organization confronted with an issue similar to an issue of a first organization to be analyzed, and that selects measures against the issue of the second organization from the data stored in the storage section. The output section outputs data for displaying the selected issue and the selected measures.

Abstract: In a semiconductor storage device that is formed on a semiconductor substrate, flows a current to a recording material formed between electrodes to change a resistance value of the recording material and store information, and flows currents of different magnitudes in a high resistance change operation and a low resistance change operation, electrodes of a plurality of memory cells are electrically connected directly or via transistors to form large electrodes, the large electrodes are connected to a feeding terminal from a power source circuit, and the large electrodes are connected to large electrodes connected to a feeding terminal from a power source connected between a plurality of memory cells different from the plurality of memory cells via inter-large electrode connection transistors.

Abstract: A computer includes a data generation unit and a storage unit which retains graph information for managing a graph configured from a plurality of vertexes and sides. The data generation unit performs acquiring a plurality of data and graph information and assuring storage regions in number equal to the number of vertexes, converting each data into an input value and setting at least one input value to a storage region corresponding to at least one vertex, executing an updating process for updating a value set to a storage region corresponding to a first vertex using the value set to the storage region corresponding to the first vertex and a value set to a storage region corresponding to a different vertex directly connected to the first vertex, and outputting a set of values set to the storage regions corresponding to the vertexes as the feature value.

Abstract: In a semiconductor recording device, a writing time as long as in the case where the number of bits to be subjected to ‘0’ writing is large even in the case where the number of bits to be subjected to ‘0’ writing in page writing is small. A population counter that controls the number of ‘0’ bits is provided. In addition, a writing driver is divided into a plurality of sub-writing drivers. In this configuration, as many sub-writing drivers as possible are driven as long as the number of ‘0’ writing bits is equal to or smaller than the maximum number of bits that can be simultaneously written.

Abstract: It is possible to realize a highly reliable semiconductor storage device using the semiconductor storage device which includes a plurality of memory chains including a plurality of memory cells connected in series and in which the memory cell is a storage element that performs rewrite using a cell transistor and current, the memory chain has a structure in which the storage elements are connected in parallel, a power-supply voltage and a ground voltage are supplied from an outside, and a voltage to be used for the rewrite of the storage element is lower than the ground voltage, and further, it is possible to realize the semiconductor storage device that has a large capacity, is capable of high-speed read and write, and can be manufactured with low cost.

Abstract: In a semiconductor storage device that is formed on a semiconductor substrate, flows a current to a recording material formed between electrodes to change a resistance value of the recording material and store information, and flows currents of different magnitudes in a high resistance change operation and a low resistance change operation, electrodes of a plurality of memory cells are electrically connected directly or via transistors to form large electrodes, the large electrodes are connected to a feeding terminal from a power source circuit, and the large electrodes are connected to large electrodes connected to a feeding terminal from a power source connected between a plurality of memory cells different from the plurality of memory cells via inter-large electrode connection transistors.

Abstract: A semiconductor storage device includes: a semiconductor substrate; a first storage unit; a second storage unit including a plurality of the first storage units formed in a first direction parallel to the semiconductor substrate; a third storage unit including a plurality of the second storage units formed in a second direction perpendicular to the first direction and parallel to the semiconductor substrate; and a fourth storage unit including a plurality of the third storage units in a third direction perpendicular to the semiconductor substrate. A plurality of contacts coupling signal lines each configured to select an address in the second direction and the semiconductor substrate, is arranged in a region in which no interference with bit lines extending in the first direction occurs. Therefore, the semiconductor storage can perform reading and writing for large capacity at a high speed, and can be manufactured at a low cost, can be achieved.

Abstract: An information processing apparatus including a memory subsystem connected to a host to perform arithmetic processing, where the host notifies a write request including data and a type of the data to the memory subsystem, and, based on a first memory, a second memory which has a size of a data erase unit, for erasing data, larger than a size of a write unit of the data and a data capacity larger than that of the first memory, and the type of the data, the memory subsystem writes random access data and data other than the random access data in different erase units of the second memory.

Abstract: When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.

Abstract: An object of this invention is to provide a semiconductor memory device capable of increasing the read transfer rate by performing the read operation in parallel while suppressing the voltage drop when a large current is passed to a memory chain and reducing a chip area by reducing the number of peripheral circuits to feed power. A semiconductor memory device according to this invention includes upper and lower electrodes in a flat plate shape, first and second select transistors extending in first and second directions respectively, and a wire arranged between the first select transistor and the second select transistor and the wire and the lower electrode are configured to be electrically insulated from each other by turning off the first select transistor (see FIG. 2).

Abstract: A semiconductor device includes a non-volatile memory unit including a plurality of chain memory arrays CY, and a control circuit that controls an access to the non-volatile memory unit. The control circuit sets, as a write area, a plurality of chain memory arrays CY arranged in a manner adjacent to each other and sets, as a dummy chain memory array DCY, a chain memory array arranged in an adjacent manner in an outer periphery of the write area. The control circuit does not perform an erasing operation on the dummy chain memory array DCY during batch-erasure of the write area. In the batch-erasure of the write area, the dummy chain memory array DCY functions to reduce an influence of heat disturbance.

Abstract: The non-volatile storage solid state drive (SSD) has non-volatile memory (NVM), random access memory (RAM) capable of being accessed at a higher speed than this NVM, and a control unit for controlling accesses to the NVM and to the RAM. The control unit stores in the NVM an address translation table that translates a logical address given to access this NVM to a physical address after dividing it into multiple tables, and stores in the RAM the multiple address translation tables-sub on RAM that have been divided into multiple tables.

Abstract: A storage controller controlling a plurality of semiconductor storage devices includes at least one first semiconductor storage device storing effective data, and at least one second semiconductor storage device not storing effective data. The storage controller includes a table for management of information identifying the second semiconductor storage device from the plurality of semiconductor storage devices, and a control unit accessing the first semiconductor storage device or the second semiconductor storage device based on an operation state of the first semiconductor storage device and the table, and dynamically changing the table according to the access.

Abstract: A semiconductor device including a nonvolatile memory cell realizes enhancement of reliability and convenience. The semiconductor device includes a nonvolatile memory unit that includes plural overwritable memory cells (CL), and a control circuit that controls access to the nonvolatile memory unit. The control circuit allocates one physical address to a chain memory array CY in the nonvolatile memory unit, for example. The control circuit performs writing to a memory cell (for example, CL0) that is apart of the chain memory array CY according to a first write command with respect to the physical address, and performs writing to a memory cell (for example, CL1) that is another part thereof according to a second write command with respect to the physical address.

Abstract: An object of this invention is to provide a semiconductor memory device capable of increasing the read transfer rate by performing the read operation in parallel while suppressing the voltage drop when a large current is passed to a memory chain and reducing a chip area by reducing the number of peripheral circuits to feed power. A semiconductor memory device according to this invention includes upper and lower electrodes in a flat plate shape, first and second select transistors extending in first and second directions respectively, and a wire arranged between the first select transistor and the second select transistor and the wire and the lower electrode are configured to be electrically insulated from each other by turning off the first select transistor (see FIG. 2).