Abstract: When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.

Abstract: An information processor includes an information processing sub-system having information processing circuits and a memory sub-system performing data communication with the information processing sub-systems, wherein the memory sub-system has a first memory, a second memory, a third memory having reading and writing latencies longer than those of the first memory and the second memory, and a memory controller for controlling data transfer among the first memory, the second memory and the third memory; graph data is stored in the third memory; the memory controller analyzes data blocks serving as part of the graph data, and performs preloading operation repeatedly to transfer the data blocks to be required next for the execution of the processing from the third memory to the first memory or the second memory on the basis of the result of the analysis.

Abstract: A first objective is to reduce performance degradation of a semiconductor storage resulting from address translation. A second objective is to reduce an increase in the manufacturing cost of the semiconductor storage resulting from address translation. A third objective is to provide the semiconductor storage with high reliability. To accomplish the above objectives, a storage area of a nonvolatile memory included in the semiconductor storage is segmented into multiple blocks, and each of the blocks is segmented into multiple pages. Then, an erase count is controlled on a page basis (109), and address translation is controlled on a block basis (108).

Abstract: An information processor includes an information processing sub-system having information processing circuits and a memory sub-system performing data communication with the information processing sub-systems, wherein the memory sub-system has a first memory, a second memory, a third memory having reading and writing latencies longer than those of the first memory and the second memory, and a memory controller for controlling data transfer among the first memory, the second memory and the third memory; graph data is stored in the third memory; the memory controller analyzes data blocks serving as part of the graph data, and performs preloading operation repeatedly to transfer the data blocks to be required next for the execution of the processing from the third memory to the first memory or the second memory on the basis of the result of the analysis.

Abstract: When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.

Abstract: An information processor includes an information processing sub-system having information processing circuits and a memory sub-system performing data communication with the information processing sub-systems, wherein the memory sub-system has a first memory, a second memory, a third memory having reading and writing latencies longer than those of the first memory and the second memory, and a memory controller for controlling data transfer among the first memory, the second memory and the third memory; graph data is stored in the third memory; the memory controller analyzes data blocks serving as part of the graph data, and performs preloading operation repeatedly to transfer the data blocks to be required next for the execution of the processing from the third memory to the first memory or the second memory on the basis of the result of the analysis.

Abstract: A semiconductor device including a nonvolatile memory cell realizes enhancement of reliability and convenience. The semiconductor device includes a nonvolatile memory unit that includes plural overwritable memory cells (CL), and a control circuit that controls access to the nonvolatile memory unit. The control circuit allocates one physical address to a chain memory array CY in the nonvolatile memory unit, for example. The control circuit performs writing to a memory cell (for example, CL0) that is apart of the chain memory array CY according to a first write command with respect to the physical address, and performs writing to a memory cell (for example, CL1) that is another part thereof according to a second write command with respect to the physical address.

Abstract: In a storage device system having a plurality of memory modules including a non-volatile memory, improved reliability and a longer life or the like is to be realized. To this end, a plurality of memory modules (STG) notifies a control circuit DKCTL0 of a write data volume (Wstg) that is actually written in an internal non-volatile memory thereof. The control circuit DKCTL0 finds a predicted write data volume (eWd) for each memory module on the basis of the write data volume (Wstg), a write data volume (Wh2d) involved in a write command that is already issued to the plurality of memory modules, and a write data volume (ntW) involved in a next write command. Then, a next write command is issued to the memory module having the smallest predicted write data volume.

Abstract: On an insulating film (41) in which a plug (43) as a lower electrode is embedded, a laminated layer pattern of an insulating film (51) made of tantalum oxide, a recording layer (52) made of Ge—Sb—Te based chalcogenide to which indium is introduced and an upper electrode film (53) made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film (51) between the recording layer (52) and the plug (43), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer (52) can be achieved. Further, by using the Ge—Sb—Te based chalcogenide to which indium is introduced as the recording layer (52), the difference in work function between the insulating film (51) and the recording layer (52) is increased, and the programming voltage of the phase change memory can be reduced.

Abstract: An information processor includes an information processing sub-system having information processing circuits and a memory sub-system performing data communication with the information processing sub-systems, wherein the memory sub-system has a first memory, a second memory, a third memory having reading and writing latencies longer than those of the first memory and the second memory, and a memory controller for controlling data transfer among the first memory, the second memory and the third memory; graph data is stored in the third memory; the memory controller analyzes data blocks serving as part of the graph data, and performs preloading operation repeatedly to transfer the data blocks to be required next for the execution of the processing from the third memory to the first memory or the second memory on the basis of the result of the analysis.

Abstract: For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.

Abstract: When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.

Abstract: On the same semiconductor substrate 1, a memory cell array in which a plurality of memory elements R having a chalcogenide-material storage layer 22 storing a high-resistance state with a high electric resistance value and a low-resistance state with a low electric resistance value by a change of an atom arrangement are disposed in a matrix is formed in a memory cell region mmry, and a semiconductor integrated circuit is formed in a logic circuit region lgc. This chalcogenide-material storage layer 22 is made of a chalcogenide material containing at least either one of Ga or In of 10.5 atom % or larger to 40 atom % or smaller, Ge of 5 atom % or larger to 35 atom % or smaller, Sb of 5 atom % or larger to 25 atom % or smaller, and Te of 40 atom % or larger to 65 atom % or smaller.

Abstract: For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.

Abstract: There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.

Abstract: For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.

Abstract: A recording layer 52 made of a chalcogenide material which stores a high-resistance state of a high electrical resistance value and a low-resistance state of a low electrical resistance value is used as a memory element RM in a memory cell region, and it is formed so that a concentration of Ga or In of a first layer 52a positioned on a lower electrode TP side of the recording layer 52 is higher than the corresponding concentration of a second layer 52b positioned on an upper electrode 53 side. For example, the recording layer is formed so that a content of Ga or In of the second layer is 5 atomic % or more smaller than that of the first layer. Also, a circuit which can reverse the voltage polarity between the upper electrode and the lower electrode in a set operation and a reset operation is provided.

Abstract: For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.

Abstract: There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.

Abstract: For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.