Patents by Inventor Ker-Hsiao Huo
Ker-Hsiao Huo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150262995Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a drain region and a channel region surrounding the drain region. A source region surrounds the channel region such that the channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and has an inner edge proximate to the drain. A resistor structure, which is made up of a curved or polygonal path of resistive material, is arranged over the drain and is coupled to the drain. The resistor structure is perimeterally bounded by the inner edge of the gate electrode.Type: ApplicationFiled: March 13, 2014Publication date: September 17, 2015Inventors: Ker Hsiao Huo, Fu-Chih Yang, Chun Lin Tsai, Yi-Min Chen, Chih-Yuan Chan
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Patent number: 9035379Abstract: A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.Type: GrantFiled: July 17, 2014Date of Patent: May 19, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ker Hsiao Huo, Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng
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Publication number: 20150072496Abstract: A method for fabricating a high voltage semiconductor transistor includes growing a first well region over a substrate having a first conductivity type, the first well region having a second type of conductivity. First, second and third portions of a second well region having the first type of conductivity are doped into the first well region. A first insulating layer is grown in and over the first well portion within the second well region. A second insulating layer is grown on the substrate over the third portion of the second well region. An anti-punch through region is doped into the first well region. A gate structure is formed on the substrate. A source region is formed in the first portion of the second well region on an opposite side of the gate structure from the first insulating layer. A drain region is formed in the first well region.Type: ApplicationFiled: November 5, 2014Publication date: March 12, 2015Inventors: Ker Hsiao HUO, Chih-Chang CHENG, Ru-Yi SU, Jen-Hao YEH, Fu-Chih YANG, Chun Lin TSAI
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Patent number: 8969913Abstract: A high voltage laterally diffused metal-oxide-semiconductor (HV LDMOS) device, particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate having at least one highly doped buried portion, a first doped well grown over the substrate, a gate structure formed on the first well, a source and a drain formed on either side of the gate structure, and a second doped well having a U-shaped cross section formed in the first well. A portion of the drain is formed over the first well outside of the second well.Type: GrantFiled: November 9, 2012Date of Patent: March 3, 2015Assignee: Taiwan Semiconductor Maufacturing Company, Ltd.Inventors: Ker Hsiao Huo, Chih-Chang Cheng, Ru-Yi Su, Jen-Hao Yeh, Fu-Chih Yang, Chun Lin Tsai
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Publication number: 20140327075Abstract: A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.Type: ApplicationFiled: July 17, 2014Publication date: November 6, 2014Inventors: Ker Hsiao HUO, Ru-Yi SU, Fu-Chih YANG, Chun Lin TSAI, Chih-Chang CHENG
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Publication number: 20140231884Abstract: A device includes a p-well region, and a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region. A P-type Buried Layer (PBL) has opposite edges in contact with the first HVNW region and the second HVNW region. An n-type buried well region is underlying the PBL. The p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL. The device further includes a n-well region in a top portion of the p-well region, an n-type source region in the n-well region, a gate stack overlapping a portion of the p-well region and a portion of the second HVNW region, and a channel region under the gate stack. The channel region interconnects the n-well region and the second HVNW region.Type: ApplicationFiled: April 30, 2014Publication date: August 21, 2014Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun-Lin Tsai
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Patent number: 8803232Abstract: A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.Type: GrantFiled: July 20, 2011Date of Patent: August 12, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ker Hsiao Huo, Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng
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Publication number: 20140139282Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.Type: ApplicationFiled: January 28, 2014Publication date: May 22, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun-Lin Tsai
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Patent number: 8704279Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.Type: GrantFiled: May 25, 2012Date of Patent: April 22, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun Lin Tsai
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Patent number: 8680616Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region.Type: GrantFiled: December 3, 2010Date of Patent: March 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Ker Hsiao Huo, Chih-Chang Cheng, Ruey-Hsin Liu
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Publication number: 20140054695Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region.Type: ApplicationFiled: November 8, 2013Publication date: February 27, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Ker Hsiao Huo, Chih-Chang Cheng, Ruey-Hsin Liu
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Publication number: 20140035035Abstract: A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.Type: ApplicationFiled: October 11, 2013Publication date: February 6, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ker Hsiao HUO, Chih-Chang CHENG, Ru-Yi SU, Jen-Hao YEH, Fu-Chih YANG, Chun Lin TSAI
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Publication number: 20140021560Abstract: Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a transistor having a gate, a source, and a drain. The source and the drain are formed in a doped substrate and are separated by a drift region of the substrate. The gate is formed over the drift region and between the source and the drain. The transistor is configured to handle high voltage conditions that are at least a few hundred volts. The high voltage semiconductor device includes a dielectric structure formed between the source and the drain of the transistor. The dielectric structure protrudes into and out of the substrate. Different parts of the dielectric structure have uneven thicknesses. The high voltage semiconductor device includes a resistor formed over the dielectric structure. The resistor has a plurality of winding segments that are substantially evenly spaced apart.Type: ApplicationFiled: July 17, 2012Publication date: January 23, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Ker Hsiao Huo, Jen-Hao Yeh, Chun-Wei Hsu
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Patent number: 8629513Abstract: A device includes a first and a second heavily doped region in a semiconductor substrate. An insulation region has at least a portion in the semiconductor substrate, wherein the insulation region is adjacent to the first and the second heavily doped regions. A gate dielectric is formed over the semiconductor substrate and having a portion over a portion of the insulation region. A gate is formed over the gate dielectric. A floating conductor is over and vertically overlapping the insulation region. A metal line includes a portion over and vertically overlapping the floating conductor, wherein the metal line is coupled to, and carries a voltage of, the second heavily doped region.Type: GrantFiled: January 14, 2011Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Yi Su, Fu-Chih Yang, Chun-Lin Tsai, Ker Hsiao Huo, Chih-Chang Cheng, Ruey-Hsin Liu
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Patent number: 8624322Abstract: Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a transistor having a gate, a source, and a drain. The source and the drain are formed in a doped substrate and are separated by a drift region of the substrate. The gate is formed over the drift region and between the source and the drain. The transistor is configured to handle high voltage conditions that are at least a few hundred volts. The high voltage semiconductor device includes a dielectric structure formed between the source and the drain of the transistor. The dielectric structure protrudes into and out of the substrate. Different parts of the dielectric structure have uneven thicknesses. The high voltage semiconductor device includes a resistor formed over the dielectric structure. The resistor has a plurality of winding segments that are substantially evenly spaced apart.Type: GrantFiled: July 17, 2012Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Ker Hsiao Huo, Jen-Hao Yeh, Chun-Wei Hsu
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Publication number: 20130313617Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.Type: ApplicationFiled: May 25, 2012Publication date: November 28, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun Lin Tsai
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Patent number: 8575694Abstract: A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.Type: GrantFiled: February 13, 2012Date of Patent: November 5, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ker Hsiao Huo, Chih-Chang Cheng, Ru-Yi Su, Jen-Hao Yeh, Fu-Chih Yang, Chun Lin Tsai
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Publication number: 20130207187Abstract: A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.Type: ApplicationFiled: February 13, 2012Publication date: August 15, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ker Hsiao HUO, Chih-Chang CHENG, Ru-Yi SU, Jen-Hao YEH, Fu-Chih YANG, Chun Lin TSAI
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Publication number: 20120299096Abstract: A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.Type: ApplicationFiled: July 20, 2011Publication date: November 29, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ker Hsiao HUO, Ru-Yi SU, Fu-Chih YANG, Chun Lin TSAI, Chih-Chang CHENG
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Publication number: 20120181629Abstract: A device includes a first and a second heavily doped region in a semiconductor substrate. An insulation region has at least a portion in the semiconductor substrate, wherein the insulation region is adjacent to the first and the second heavily doped regions. A gate dielectric is formed over the semiconductor substrate and having a portion over a portion of the insulation region. A gate is formed over the gate dielectric. A floating conductor is over and vertically overlapping the insulation region. A metal line includes a portion over and vertically overlapping the floating conductor, wherein the metal line is coupled to, and carries a voltage of, the second heavily doped region.Type: ApplicationFiled: January 14, 2011Publication date: July 19, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Yi Su, Fu-Chih Yang, Chun-Lin Tsai, Ker Hsiao Huo, Chih-Chang Cheng, Ruey-Hsin Liu