Abstract: A computer-implemented method, system and computer program product for recommending design changes in designing a digital integrated circuit. An analysis of the digital integrated circuit being designed is performed, where the result of such an analysis involves violations being identified and stored. A stored violation, such as a cross-domain, cross-hierarchy and multi-cycle violation, may then be analyzed to identify a root cause of the violation using a rule. Such a rule may be used for triaging various failures in the cross-domain, cross-hierarchy and/or multi-cycle violation of the digital integrated circuit. A design change in the design of the digital integrated circuit may then be recommended based on the identified root cause of the violation. In this manner, the root cause of failures are effectively identified in the design of digital integrated circuits using an offline analysis of cross-domain, cross-hierarchy and/or multi-cycle violations using a rules-based approach.

Abstract: The efficiency of electronic design automation is increased by building, as an electronic data structure, a timing graph characterizing a putative integrated circuit design; identifying at least one of an edge and a node in the timing graph that requires canonical timing adjustment; and electronically calculating a deterministic timing adjustment for each of a plurality of corner cases. Based on the calculated deterministic timing adjustment for each of the plurality of corner cases, the canonical timing adjustment is determined for the at least one of an edge and a node; the canonical timing adjustment is applied to the timing graph; and the timing graph is updated based on the application of the canonical timing adjustment.

Abstract: The efficiency of electronic design automation is increased by building, as an electronic data structure, a timing graph characterizing a putative integrated circuit design; identifying at least one of an edge and a node in the timing graph that requires canonical timing adjustment; and electronically calculating a deterministic timing adjustment for each of a plurality of corner cases. Based on the calculated deterministic timing adjustment for each of the plurality of corner cases, the canonical timing adjustment is determined for the at least one of an edge and a node; the canonical timing adjustment is applied to the timing graph; and the timing graph is updated based on the application of the canonical timing adjustment.

Abstract: A method, computer program product, and system for calculating an input timing slack at an input to a latch by subtracting an input arrival time to the latch from an input required arrival time, calculating an output timing slack at an output to the latch by subtracting an output arrival time of the latch from an output required arrival time from the latch, performing cycle stealing to improve the output timing slack by modifying the input required arrival time and the output arrival time, reducing the output timing slack by a pessimism amount, performing optimization in the integrated circuit to improve the input timing slack and the output timing slack, and increasing the output timing slack by the pessimism amount.

Abstract: Embodiments of the present invention disclose a method, computer program product, and system for parallel access to an electronic design automation (EDA) application. The computer receives a request to access an electronic design automation (EDA) application from at least two user computing device and authenticates a user associated with each of the requests from the at least two user computing devices to access the EDA application. The computer determines a level of access to be granted to each of the user of the at least two user computing devices and creates a parallel connection to each of the at least user computing device based on the determined level of access granted to each of the users. The computer retrieves data to be transmitted to each of the at least user computing device to be displayed on each of the user computing devices and stores the data in a memory unit.

Abstract: To increase the efficiency of electronic design automation, in a putative electronic logic circuit design, at least one transparent latch is identified as a candidate for slack stealing. An initial timing slack, available for stealing, and associated with the at least one transparent latch, is determined. Responsive to a determination that the initial timing slack available for stealing is insufficient, it is determined whether the initial timing slack available for stealing is on a feedback path. If so, responsive to determining that the initial timing slack available for stealing is on the feedback path, the initial timing slack available for stealing is replaced with a next worse slack.

Abstract: To increase the efficiency of electronic design automation, in a putative electronic logic circuit design, at least one transparent latch is identified as a candidate for slack stealing. An initial timing slack, available for stealing, and associated with the at least one transparent latch, is determined. Responsive to a determination that the initial timing slack available for stealing is insufficient, it is determined whether the initial timing slack available for stealing is on a feedback path. If so, responsive to determining that the initial timing slack available for stealing is on the feedback path, the initial timing slack available for stealing is replaced with a next worse slack.

Abstract: An electronic design automation (EDA) data processing system includes a version graph database and a controller. The version graph database stores a plurality of different versions of graph data sets. Each graph data set corresponds to a respective circuit component located at a given hierarchical level of a semiconductor chip design and each graph data set tagged with a version identifier (ID) indicating the version thereof. The controller determines a hierarchical circuit included in the semiconductor chip and determines a plurality of targeted circuit components that define the hierarchical circuit. The controller determines targeted graph data sets from the versions graph database that correspond to the targeted circuit components, and obtains the targeted graph data sets having matching version IDs such that the targeted graph data sets are the same version.

Abstract: A system and method of performing variable accuracy incremental timing analysis in integrated circuit development includes generating a timing graph for interconnected components. The timing graph represents each pin as a node and each interconnection as an arc. A first node or arc is selected. First-level timing values are obtained for the first node or arc using a first timing model that provides a first level of accuracy. n timing models with corresponding n levels of accuracy are pre-selected. The first-level timing values are copied as second-level timing values and as timing values for every other one of the n levels of accuracy for the first node or arc. A second node or arc downstream from the first node or arc is selected. Second-level timing values for the second node or arc are obtained using a second timing model that provides a second level of accuracy.

Abstract: A system and method of performing variable accuracy incremental timing analysis in integrated circuit development includes generating a timing graph for interconnected components. The timing graph represents each pin as a node and each interconnection as an arc. A first node or arc is selected. First-level timing values are obtained for the first node or arc using a first timing model that provides a first level of accuracy. n timing models with corresponding n levels of accuracy are pre-selected. The first-level timing values are copied as second-level timing values and as timing values for every other one of the n levels of accuracy for the first node or arc. A second node or arc downstream from the first node or arc is selected. Second-level timing values for the second node or arc are obtained using a second timing model that provides a second level of accuracy.

Abstract: Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In one example according to aspects of the present disclosure, a computer-implemented method is provided. The method comprises performing an initial statistical static timing analysis of the integrated circuit to create a parameterized model of the integrated circuit for a plurality of paths using a plurality of timing corners to calculate a timing value for each of the plurality of paths, each of the plurality of timing corners representing a set of timing performance parameters. The method further comprises determining at least one worst timing corner from the parameterized model for each of the plurality of paths based on the initial statistical static timing analysis and calculated timing value for each of the plurality of paths. The method also comprises performing a subsequent analysis of the integrated circuit using the at least one worst timing corner.

Abstract: A method, computer program product, and system for calculating an input timing slack at an input to a latch by subtracting an input arrival time to the latch from an input required arrival time, calculating an output timing slack at an output to the latch by subtracting an output arrival time of the latch from an output required arrival time from the latch, performing cycle stealing to improve the output timing slack by modifying the input required arrival time and the output arrival time, reducing the output timing slack by a pessimism amount, performing optimization in the integrated circuit to improve the input timing slack and the output timing slack, and increasing the output timing slack by the pessimism amount.

Abstract: A method, computer program product, and system for calculating an input timing slack at an input to a latch by subtracting an input arrival time to the latch from an input required arrival time, calculating an output timing slack at an output to the latch by subtracting an output arrival time of the latch from an output required arrival time from the latch, performing cycle stealing to improve the output timing slack by modifying the input required arrival time and the output arrival time, reducing the output timing slack by a pessimism amount, performing optimization in the integrated circuit to improve the input timing slack and the output timing slack, and increasing the output timing slack by the pessimism amount.

Abstract: A system and method involves partitioning a design of an integrated circuit into two or more hierarchical levels. A lowest level includes macros and a higher level includes some or all of the macros. Each of the macros includes two or more components. A macro timing model corresponding with each of the macros indicates a delay through the macro. The macro timing model corresponding with ones of the macros that are part of the higher level are loaded to perform higher-level timing analysis, which indicates a delay through the ones of the macros that are part of the higher level. Modified macro timing models corresponding with one or more of the macros are generated, and only the modified macro timing models associated with the macros that are part of the higher level modify corresponding loaded macro timing models to continue the higher-level timing analysis.

Abstract: A method, computer program product, and system for calculating an input timing slack at an input to a latch by subtracting an input arrival time to the latch from an input required arrival time, calculating an output timing slack at an output to the latch by subtracting an output arrival time of the latch from an output required arrival time from the latch, performing cycle stealing to improve the output timing slack by modifying the input required arrival time and the output arrival time, reducing the output timing slack by a pessimism amount, performing optimization in the integrated circuit to improve the input timing slack and the output timing slack, and increasing the output timing slack by the pessimism amount.

Abstract: Embodiments of the present invention disclose a method, computer program product, and system for parallel access to an electronic design automation (EDA) application. The computer receives a request to access an electronic design automation (EDA) application from at least two user computing device and authenticates a user associated with each of the requests from the at least two user computing devices to access the EDA application. The computer determines a level of access to be granted to each of the user of the at least two user computing devices and creates a parallel connection to each of the at least user computing device based on the determined level of access granted to each of the users. The computer retrieves data to be transmitted to each of the at least user computing device to be displayed on each of the user computing devices and stores the data in a memory unit.

Abstract: Embodiments of the present invention disclose a method, computer program product, and system for parallel access to an electronic design automation (EDA) application. The computer receives a request to access an electronic design automation (EDA) application from at least two user computing device and authenticates a user associated with each of the requests from the at least two user computing devices to access the EDA application. The computer determines a level of access to be granted to each of the user of the at least two user computing devices and creates a parallel connection to each of the at least user computing device based on the determined level of access granted to each of the users. The computer retrieves data to be transmitted to each of the at least user computing device to be displayed on each of the user computing devices and stores the data in a memory unit.

Abstract: Creating an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Abstract: The computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Abstract: A design and timing model for at least one circuit path of at least a portion of an IC design is loaded into a computer. At least one canonical clock variable associated with the model is defined; it includes at least one source of variation. The computer is used to perform an SSTA of the at least one circuit path, based on the design and timing model and the at least one canonical clock variable, to obtain slack canonical data. A clock period is projected, based on the slack canonical data, such that a cycle time canonical is projected to a different space than a logic canonical. Results of the SSTA and the projected clock period are output to determine performance compliance. Efficient operation of the computer is enhanced by analyzing a slack vector in a single timing run, loaded once, and multithreading timing propagation.