Abstract: The timing analysis of an integrated chip component using dynamic load sensitive timing feedback constraints maintaining the timing accuracy for all the boundary paths is achieved by capturing a reduced order representation for parasitic load within a component for each of its primary input and primary output along with sensitivities of the arrival time, the slew and the required arrival time to the load representation at the component parent level of hierarchy as part of generating load sensitive feedback constraints. During the out-of-context timing closure of the component, the base load representation and the sensitivities, and an updated load representation enables the calculation of the updated boundary constraint for an accurate timing analysis. The accuracy improvement increases a chip designer productivity during timing closure resulting in a shortened time to take the chip design through timing closure to manufacturing.

Abstract: Improving automated timing analysis includes: generating a directed acyclic graph for an input netlist, generating a second order graph distance metric based at least on the directed acyclic graph, and scheduling a timing calculation for a set of nodes of the input netlist based at least on the second order graph distance metric.

Abstract: The method includes identifying, by one or more computer processors, a location that corresponds to an integrated circuit chip on a wafer. The method further includes identifying, by one or more computer processors, an on-chip variation of the integrated circuit chip. The method further includes determining, by one or more computer processes, a desired voltage for the integrated circuit chip based upon the identified on-chip variation of the integrated circuit chip. The method further includes adjusting, by one or more computer processors, the voltage of the integrated circuit chip via a voltage regulated on the integrated circuit chip based upon the determined desired voltage.

Abstract: Timing window manipulation for noise reduction includes: selecting a path of a circuit design having a timing violation from a timing analysis of a victim window; determining an aggressor net coupled to a victim net along the path; determining a propagation path through the determined aggressor net; propagating a victim window value backward through the propagation path, the victim window value associated with the victim net; and modifying circuit characteristics of the circuit design within a switching window associated with the aggressor net based at least on the propagated victim window value.

Abstract: Timing window manipulation for noise reduction includes: selecting a path of a circuit design having a timing violation from a timing analysis of a victim window; determining an aggressor net coupled to a victim net along the path; determining a propagation path through the determined aggressor net; propagating a victim window value backward through the propagation path, the victim window value associated with the victim net; and modifying circuit characteristics of the circuit design within a switching window associated with the aggressor net based at least on the propagated victim window value.

Abstract: Improving automated timing analysis includes: generating a directed acyclic graph for an input netlist, generating a second order graph distance metric based at least on the directed acyclic graph, and scheduling a timing calculation for a set of nodes of the input netlist based at least on the second order graph distance metric.

Abstract: A method for controlling a circuit, the method comprises performing a first timing analysis of an digital integrated design, identifying a critical path in the digital integrated design that is dependent on a parameter, modifying the digital integrated design by inserting a first delay inducing circuit, running a second timing analysis on the modified digital integrated design to determine whether a delay induced by the first delay inducing circuit meets a timing requirement of the digital integrated design, and saving the delay induced by the first delay inducing circuit with an association to the parameter in a timing library responsive to determining that the delay induced by the first delay inducing circuit meets the timing requirement of the digital integrated design.

Abstract: Disclosed are a system and a method for performing a timing analysis of an integrated circuit (IC). An internal timing constraint of a logic device in a first signal pathway of a hierarchical entity in an IC design is determined based on a reference value and, if necessary, on library information. A first boundary timing constraint associated with the first signal pathway is derived based on the internal timing constraint and a second boundary timing constraint associated with the first signal pathway is derived based on the first boundary timing constraint and a target slack value for the internal timing constraint. A static timing analysis is performed using the second boundary timing constraint. Based on the analysis, a timing abstraction for the hierarchical entity is generated. A timing model for the IC design is generated using the timing abstraction and other timing abstractions for other hierarchical entities in the design.

Abstract: According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.

Abstract: Methods and systems receive an integrated circuit design into a computerized device and perform an analysis of the integrated circuit design to identify characteristics of physical features of portions of the integrated circuit design. Such methods and systems determine whether to look up sensitivity of a timing value of a portion of the integrated circuit design to manufacturing process variables, voltage variables, and temperature variables (PVT variables) by: evaluating relationships between the characteristics of physical features of the portion of the integrated circuit design to generate an indicator value; and, based on whether the indicator value is within a table usage filter value range, either: calculating the sensitivity of the timing value to the PVT variables; or looking up a previously determined sensitivity of the timing value to the PVT variables from a look-up table.

Abstract: Systems and methods compute a mean timing value of an integrated circuit design for variables using a first timing calculation of relatively higher accuracy; and calculate a first timing value of the integrated circuit design for the variables, using a second timing calculation having a relatively lower accuracy. Such systems and methods calculate second timing values of the integrated circuit design for additional sets of variables using the second timing calculation; and calculate finite differences of each of the second timing values to the first timing value. Thus, these systems and methods calculate a statistical sensitivity of the first timing value to the additional sets of variables based on the finite differences. Further, such systems and methods calculate a statistical sensitivity of the mean timing value to the additional sets of values based on the statistical sensitivity of the first timing value to the additional sets of values.

Abstract: Methods and systems receive an integrated circuit design into a computerized device and perform an analysis of the integrated circuit design to identify characteristics of physical features of portions of the integrated circuit design. Such methods and systems determine whether to look up sensitivity of a timing value of a portion of the integrated circuit design to manufacturing process variables, voltage variables, and temperature variables (PVT variables) by: evaluating relationships between the characteristics of physical features of the portion of the integrated circuit design to generate an indicator value; and, based on whether the indicator value is within a table usage filter value range, either: calculating the sensitivity of the timing value to the PVT variables; or looking up a previously determined sensitivity of the timing value to the PVT variables from a look-up table.

Abstract: Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In one example according to aspects of the present disclosure, a computer-implemented method is provided. The method comprises performing an initial statistical static timing analysis of the integrated circuit to create a parameterized model of the integrated circuit for a plurality of paths using a plurality of timing corners to calculate a timing value for each of the plurality of paths, each of the plurality of timing corners representing a set of timing performance parameters. The method further comprises determining at least one worst timing corner from the parameterized model for each of the plurality of paths based on the initial statistical static timing analysis and calculated timing value for each of the plurality of paths. The method also comprises performing a subsequent analysis of the integrated circuit using the at least one worst timing corner.

Abstract: A method, system, and computer program product to perform dynamic voltage frequency scaling of an integrated circuit include performing statistical timing analysis using a canonical form of a clock, the canonical form of the clock being a function of variability in voltage. Obtaining a canonical model expressing timing slack at each test location of the integrated circuit is as a function of one or more sources of variability, one of the one or more sources of variability being voltage, and performing the dynamic voltage-frequency scaling based on selecting at least one of a clock period and the voltage using the canonical model.

Abstract: According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.

Abstract: Systems and methods compute a mean timing value of an integrated circuit design for variables using a first timing calculation of relatively higher accuracy; and calculate a first timing value of the integrated circuit design for the variables, using a second timing calculation having a relatively lower accuracy. Such systems and methods calculate second timing values of the integrated circuit design for additional sets of variables using the second timing calculation; and calculate finite differences of each of the second timing values to the first timing value. Thus, these systems and methods calculate a statistical sensitivity of the first timing value to the additional sets of variables based on the finite differences. Further, such systems and methods calculate a statistical sensitivity of the mean timing value to the additional sets of values based on the statistical sensitivity of the first timing value to the additional sets of values.

Abstract: The timing analysis of an integrated chip component using dynamic load sensitive timing feedback constraints maintaining the timing accuracy for all the boundary paths is achieved by capturing a reduced order representation for parasitic load within a component for each of its primary input and primary output along with sensitivities of the arrival time, the slew and the required arrival time to the load representation at the component parent level of hierarchy as part of generating load sensitive feedback constraints. During the out-of-context timing closure of the component, the base load representation and the sensitivities, and an updated load representation enables the calculation of the updated boundary constraint for an accurate timing analysis. The accuracy improvement increases a chip designer productivity during timing closure resulting in a shortened time to take the chip design through timing closure to manufacturing.

Abstract: According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.

Abstract: According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.

Abstract: The method includes identifying, by one or more computer processors, a location that corresponds to an integrated circuit chip on a wafer. The method further includes identifying, by one or more computer processors, an on-chip variation of the integrated circuit chip. The method further includes determining, by one or more computer processes, a desired voltage for the integrated circuit chip based upon the identified on-chip variation of the integrated circuit chip. The method further includes adjusting, by one or more computer processors, the voltage of the integrated circuit chip via a voltage regulated on the integrated circuit chip based upon the determined desired voltage.