Abstract: Computing accurately and effectively the impact of clock skew on statistical slack in the presence of statistically variable timing quantities that accounts for both common path credit in the common portion of the clock tree, and RSS credit in the non-common of the clock tree. The clock skew is measured on a per launch and capture path-pair basis as a function of on the post-CPPR path-specific slack (including RSS credit), total mean value of latch-to-latch delay, RSS value of random latch-to-latch delay, test guard time and test adjust. The method includes: performing an initial block-based SSTA including CPPR analysis; selecting at least one launch and capture path-pair for skew analysis; for the at least one path pair, recording post CPPR slack, total mean value of latch-to-latch delay, RSS value of latch to latch delay, test guard time and test adjust; and quantifying the impact of clock skew on statistical slack thereof.

Abstract: A method for performing a hierarchical statistical timing analysis of an integrated circuit (IC) chip design by abstracting one or more macros of the design. The method includes performing a statistical static timing analysis of at least one macro; performing a statistical abstraction of the macro to obtain a statistical abstract model of the macro timing characteristics; applying the statistical abstract model as the timing model for each occurrence of the macro leading to a simplified IC chip design; and performing a hierarchical statistical timing analysis of the simplified chip design. The method achieves a context aware statistical abstraction, where a generated statistical abstract model is instantiated for each macro of the chip during statistical static timing analysis at the chip level, providing a compressed and pruned statistical timing abstraction and reducing the model-size during the statistical abstraction.

Abstract: A computer system for partitioning the columns of a matrix A. The computer system includes a processor and a memory unit coupled to the processor. Program code in the memory unit, when executed by the processor, implements the method. Matrix A is provided in a memory device and has n columns and m rows; wherein n is an integer of at least 3; and wherein m is an integer of at least 1. The n columns is partitioned into a closed group of p clusters, p being a positive integer of at least 2 and less than n. The partitioning includes an affinity -based merging of clusters of pairs of clusters of the matrix A based on an affinity between the clusters in each pair of clusters being merged. Each cluster consists of one or more columns of matrix A. The p clusters are stored in a computer-readable storage device.

Abstract: A system and method for the adjustment of history based delay variation during static timing analysis of an integrated circuit design. The method may include obtaining information through sources of variability of history based components of delay variability, and a relationship between the sources of variability and one or more bounded device histories. Then, inputting history bounds for at least one signal of the integrated circuit design, and computing and propagating history bounds through at least one first segment of the integrated circuit design to at least one signal of the integrated circuit design. Further, the method may include evaluating from at least one of the propagated history bounds, device history bounds for at least one second segment of the integrated circuit design, and based on the evaluated device history bounds, adjusting at least one of a value of the history based delay variability and propagation of timing.

Abstract: A method for loading checkpoint timing in an environment where the boundary arrival times, slews, required arrival times, or loads differ from the checkpoint run. A timing checkpoint file generated for one or more hierarchical modules, during which each input is assigned a unique phase tag. The association of unique phase tags allows subsequent restart analyses to efficiently adjust the checkpoint timing in relation to the restart timing environment. In the restart run, one or more such checkpoint files is read, during which an initial propagation of arrival, required arrivals and slew times are performed, followed by a local re-update based on adjusted arrival times and the required arrival times. Finally, if multiple hierarchical modules are updated, a global recalculation of timing values is performed based on a slack change threshold in order to determine whether any new timing failures have been introduced.

Abstract: A method and a system for validating clock skews during a hierarchical static timing analysis of a chip or multi-chip package. Each pair of clock inputs of a hierarchical module bounds the allowable clock skew, creating new relative constraints on clock input arrival times propagated to those clock inputs. One embodiment is based on asserted arrival times and a maximum of computed slack values at said clock inputs, while a second embodiment is based on asserted arrival times and a minimum of downstream test slack values. The method further converts module clock assertions into a set of relative timing constraints to allow a hierarchical timing sign-off even in circumstances where absolute timing arrivals are not totally known at the time of module analysis.

Abstract: A method for partitioning the columns of a matrix A. The method includes providing the matrix A in a memory device of a computer system. The matrix A has n columns and m rows, wherein n is an integer of at least 3, and wherein m is an integer of at least 1. The method further includes executing an algorithm by a processor of the computer system. Executing the algorithm includes partitioning the n columns of the matrix A into a closed group of p clusters, wherein p is a positive integer of at least 2 and less than n, wherein the partitioning includes an affinity-based merging of clusters of the matrix A, and wherein each cluster is a collection of one or more columns of A.

Abstract: A system and method for adjustment of modeled timing data variation as a function of past state and/or switching history during static timing analysis. One illustrative embodiment may include inputting and asserting at least one of initial signal history bound and explicit device history bound constraints for at least one signal of a circuit design and evaluating for a segment processed during a forward propagation of block based static timing analysis whether any input signal to a current segment has a bounded history, at least one of propagated and asserted. The method may further include evaluating for the segment whether history bounds are downstream from a gating restriction, and processing a next segment until there are no further segments.

Abstract: A system and method for the adjustment of history based delay variation during static timing analysis of an integrated circuit design. The method may include obtaining information through sources of variability of history based components of delay variability, and a relationship between the sources of variability and one or more bounded device histories. Then, inputting history bounds for at least one signal of the integrated circuit design, and computing and propagating history bounds through at least one first segment of the integrated circuit design to at least one signal of the integrated circuit design. Further, the method may include evaluating from at least one of the propagated history bounds, device history bounds for at least one second segment of the integrated circuit design, and based on the evaluated device history bounds, adjusting at least one of a value of the history based delay variability and propagation of timing.

Abstract: A method of optimizing timing of signals within an integrated circuit design using proxy slack values propagates signals through the integrated circuit design to output timing signals. For early mode timing analysis, the method sets an early proxy slack value to zero if the late slack value is less than zero. Otherwise, if the late slack value is not less than zero, the method restricts the early proxy slack value to a maximum of the early slack value and the negative of the late slack value. To the contrary, for late mode timing analysis, the method sets a late proxy slack value to zero if the early slack value is less than zero. Otherwise, if the early proxy slack value is not less than zero, the method restricts the late proxy slack value to a maximum of the late slack value and the negative of the early slack value.

Abstract: A method and system for decreasing processing time in multi-corner static timing analysis. In one embodiment, parameters are ordered in a parameter order by decreasing magnitude of impact on variability of timing. In one example, a decreasing parameter order is utilized to order slack cutoff values that are assigned across a parameter process space. In another example, a decreasing parameter order is utilized to perform a multi-corner timing analysis on one or more dependent parameters in an independent fashion.

Abstract: A method and system for reducing a number of paths to be analyzed in a multi-corner static timing analysis. An estimated upper slack variation based on a non-common path delay for a racing path is utilized in determining if a multi-corner static timing analysis may be bypassed for a racing path. In another example, an estimated maximum RSS credit based on a total delay for a racing path is utilized in determining if a multi-corner static timing analysis may be bypassed for a racing path.

Abstract: A method for performing a hierarchical statistical timing analysis of an integrated circuit (IC) chip design by abstracting one or more macros of the design. The method includes performing a statistical static timing analysis of at least one macro; performing a statistical abstraction of the macro to obtain a statistical abstract model of the macro timing characteristics; applying the statistical abstract model as the timing model for each occurrence of the macro leading to a simplified IC chip design; and performing a hierarchical statistical timing analysis of the simplified chip design. The method achieves a context aware statistical abstraction, where a generated statistical abstract model is instantiated for each macro of the chip during statistical static timing analysis at the chip level, providing a compressed and pruned statistical timing abstraction and reducing the model-size during the statistical abstraction.

Abstract: A method for loading checkpoint timing in an environment where the boundary arrival times, slews, required arrival times, or loads differ from the checkpoint run. A timing checkpoint file generated for one or more hierarchical modules, during which each input is assigned a unique phase tag. The association of unique phase tags allows subsequent restart analyses to efficiently adjust the checkpoint timing in relation to the restart timing environment. In the restart run, one or more such checkpoint files is read, during which an initial propagation of arrival, required arrivals and slew times are performed, followed by a local re-update based on adjusted arrival times and the required arrival times. Finally, if multiple hierarchical modules are updated, a global recalculation of timing values is performed based on a slack change threshold in order to determine whether any new timing failures have been introduced.

Abstract: A method and a system for validating clock skews during a hierarchical static timing analysis of a chip or multi-chip package. Each pair of clock inputs of a hierarchical module bounds the allowable clock skew, creating new relative constraints on clock input arrival times propagated to those clock inputs. One embodiment is based on asserted arrival times and a maximum of computed slack values at said clock inputs, while a second embodiment is based on asserted arrival times and a minimum of downstream test slack values. The method further converts module clock assertions into a set of relative timing constraints to allow a hierarchical timing sign-off even in circumstances where absolute timing arrivals are not totally known at the time of module analysis.

Abstract: A method and a system for conducting a static timing analysis on a circuit having a plurality of point-to-point delay constraints between two points of the circuit, in which two conservative and two optimistic user defined tests are derived for all types of the point-to-point delay constraints. The method shows that when a conservative test is performed without introducing any special tags, then it is found that the point-to-point constraint is satisfied. On the other hand, when the optimistic test fails without any special tags, it is determined that the point-to-point constraint is bound to fail if special tags are introduced, in which case, they are to be introduced only when an exact slack is desired. Finally, for anything in between, a real analysis with special tags or path tracing is required. Based on the topology of the graph, arrival time based tests may be tighter in some situations, while the required arrival time based tests, may be tighter in others.

Abstract: Run-time reduction is achieved in timing performance of a logical design, such as a digital integrated circuit. A portion of the logical design that is expected to be stable with respect to timing performance, such as a clock tree, is identified. Timing sensitivities, including sensitivities to sources of variability, of the identified portion of the logical design are determined at a given instant. The timing sensitivities of the identified portion of the logical design are saved for re-use. The saved timing sensitivities are re-used throughout the timing analysis and in subsequent timing analyses.

Abstract: A method and system for decreasing processing time in multi-corner static timing analysis. In one embodiment, slack cutoff values are assigned across a parameter process space. For example, a slack cutoff value is assigned to each parameter in a process space by determining an estimated maximum slack change between a starting corner and any other corner in a corresponding process sub-space. In another embodiment, parameters are ordered in a parameter order by decreasing magnitude of impact on variability of timing.

Abstract: A method of performing node-based static timing analysis on a digital network and a program storage device for implementing the method, wherein the method comprises partitioning timing delays in the digital network into portions attributable to a factor of interest and portions attributable to other factors; multiplying the timing delays by different weights based on the factor of interest to produce weighted timing delays; and using the multiplied timing delays to determine a relative impact of the factor of interest on the various paths in the digital network. The method further comprises setting arrival times of timing signals at digital network path start points to zero and identifying digital network paths whose timing delays are dominated by a particular factor of interest. The different weights comprise any of a positive weight, a negative weight, and a zero weight.

Abstract: A method of optimizing timing of signals within an integrated circuit design using proxy slack values propagates signals through the integrated circuit design to output timing signals. For early mode timing analysis, the method sets an early proxy slack value to zero if the late slack value is less than zero. Otherwise, if the late slack value is not less than zero, the method restricts the early proxy slack value to a maximum of the early slack value and the negative of the late slack value. To the contrary, for late mode timing analysis, the method sets a late proxy slack value to zero if the early slack value is less than zero. Otherwise, if the early proxy slack value is not less than zero, the method restricts the late proxy slack value to a maximum of the late slack value and the negative of the early slack value.