Abstract: A spread spectrum clock generator which includes a pulse train generator circuit and a modulating circuit configured to produce a modulating signal relating to a time derivative of an output of the pulse train generator circuit. In one embodiment the modulating circuit includes a active differentiator circuit and in another embodiment the modulating circuit includes a passive differentiator circuit. A modulator is included which is configured to produce a spread spectrum clock output which is frequency modulated by the modulating signal.

Abstract: A spread spectrum clock generator which includes a pulse train generator circuit and a modulating circuit configured to produce a modulating signal relating to a time derivative of an output of the pulse train generator circuit. In one embodiment the modulating circuit includes a active differentiator circuit and in another embodiment the modulating circuit includes a passive differentiator circuit. A modulator is included which is configured to produce a spread spectrum clock output which is frequency modulated by the modulating signal.

Abstract: A spread spectrum clock generator which includes a pulse train generator circuit and a modulating circuit configured to produce a modulating signal relating to a time derivative of an output of the pulse train generator circuit. In one embodiment the modulating circuit includes a active differentiator circuit and in another embodiment the modulating circuit includes a passive differentiator circuit. A modulator is included which is configured to produce a spread spectrum clock output which is frequency modulated by the modulating signal.

Abstract: A clock generator circuit for producing a clock output having a controlled duty cycle is disclosed. A bi-stable circuit provides the clock output which is switchable to a first state in response to an edge of the input clock signal and to a second state in response to a feedback signal. A duty cycle detection circuit is configured to source a current to a node and to sink a current from the node depending upon the output clock state. A capacitor is connected to receive a duty cycle current relating to the current at the node, with a comparator circuit being configured to sense a voltage on the capacitor and to produce the feedback signal when the voltage is at a selected level.

Abstract: A spread spectrum clock generator which includes a pulse train generator circuit and a modulating circuit configured to produce a modulating signal relating to a time derivative of an output of the pulse train generator circuit. In one embodiment the modulating circuit includes a active differentiator circuit and in another embodiment the modulating circuit includes a passive differentiator circuit. A modulator is included which is configured to produce a spread spectrum clock output which is frequency modulated by the modulating signal.

Abstract: A spread spectrum clock generator which includes a pulse train generator circuit and a modulating circuit configured to produce a modulating signal relating to a time derivative of an output of the pulse train generator circuit. In one embodiment the modulating circuit includes a active differentiator circuit and in another embodiment the modulating circuit includes a passive differentiator circuit. A modulator is included which is configured to produce a spread spectrum clock output which is frequency modulated by the modulating signal.

Abstract: A clock generator circuit for producing a clock output having a controlled duty cycle is disclosed. A bi-stable circuit provides the clock output which is switchable to a first state in response to an edge of the input clock signal and to a second state in response to a feedback signal. A duty cycle detection circuit is configured to source a current to a node and to sink a current from the node depending upon the output clock state. A capacitor is connected to receive a duty cycle current relating to the current at the node, with a comparator circuit being configured to sense a voltage on the capacitor and to produce the feedback signal when the voltage is at a selected level.

Abstract: The invention relates to a regulator with an under-voltage lock-out (UVLO) circuit and a reference generator circuit (e.g., a band-gap reference). The UVLO circuit includes an internal band-gap reference circuit and a comparison circuit. The UVLO circuit compares an input voltage with the output of the internal band-gap reference circuit to selectively enable the regulator. The output of the internal band-gap reference circuit is also employed to power the reference generator circuit. The reference generator circuit provides a reference signal which is employed to control steady-state regulation. The regulator also includes an operational amplifier circuit for increasing the drive and/or voltage level of the internal band-gap reference circuit output.

Abstract: The invention relates to a regulator with a reference generator circuit (e.g., a band-gap reference) and a reference generator power selector. The reference generator power selector selectively powers the reference generator circuit from an input power signal during start-up and from a regulated power signal during steady-state operation. The reference generator power selector may also select from multiple regulated power signals during steady-state operation.

Abstract: A phase-locked loop (PLL) frequency synthesizer is described which incorporates a fractional pulse swallowing circuit. The fractional pulse swallowing circuit does not add or delete pulses but extends or shortens pulses by a fractional amount. This avoids large phase errors generated by a phase detector in the PLL. In the preferred embodiment, the PLL uses a voltage controlled oscillator (VCO) formed of a ring oscillator. The outputs of the stages of the ring oscillator are applied to input terminals of a multiplexer. The multiplexer is controlled at certain times to output a different tapped signal from the ring oscillator to effectively adjust the phase of the signal output from the multiplexer. By so controlling the multiplexer, fractional pulses are subtracted or added at intervals to either increase or decrease the average frequency of the signal output from the multiplexer. The output of the VCO is fed back to the input of a phase detector along with a reference frequency.