Abstract: A method for robust demodulation of the communications system in presence of sparse severe impulse noise is presented. In this invention, the application of impulse noise removal in orthogonal frequency domain multiplexing systems is investigated. The impulse noise causes catastrophic accuracy degradation at the output of the fast Fourier transform operations at the receiver. In this invention, an impulse noise identification scheme is proposed to determine the presence of the impulse noise. An impulse noise value search algorithm at known location based on the steepest descent method, an impulse noise location algorithm, and a novel iterative impulse error correction scheme are presented to remove the sparse error and demodulate the transmitted symbols accurately.

Abstract: The present invention relates to the design and implementation of parallel pipelined circuits for the fast Fourier transform (FFT). In this invention, an efficient way of designing FFT circuits using folding transformation and register minimization techniques is proposed. Based on the proposed scheme, novel parallel-pipelined architectures for the computation of complex fast Fourier transform are derived. The proposed architecture takes advantage of under utilized hardware in the serial architecture to derive L-parallel architectures without increasing the hardware complexity by a factor of L. The proposed circuits process L consecutive samples from a single-channel signal in parallel. The operating frequency of the proposed architecture can be decreased which in turn reduces the power consumption. The proposed scheme is general and suitable for applications such as communications, biomedical monitoring systems, and high speed OFDM systems.

Abstract: Variable Rate Congestion Controllers and methods for implementing Variable Rate Congestion Control are presented. An efficient and systematic method for performing variable rate network congestion control is presented. A selection mechanism is selected such that the end result for the network congestion control is that each variable rate network flow suffers approximately equally through the congested node. This achieves a fair policy of implementing Quality of Service for variable rate streaming data.

Abstract: Secure Variable Data Rate Transceivers and methods for implementing Secure Variable Data Rate are presented. An efficient and systematic method and circuit for implementing secure variable data rate transceivers are presented. The SVDR method is based on block ciphers. An index method is presented for minimizing transmission overhead. This allows SVDR to achieve higher security by using the full ciphermode stream.

Abstract: The present invention relates to data processing techniques in multi-channel data transmission systems. In this invention, a novel approach is proposed to deal with FEXT interferences in the application of high/ultra-high speed Ethernet systems. Compared with the traditional FEXT cancellation approaches, the proposed FEXT canceller can deal with the non-causal part of FEXT, and thus can achieve better cancellation performance. Instead of using the conventional DFE, structure, TH precoding technique is incorporated into the proposed design to alleviate the error propagation problem. The resulting FEXT cancellers do not contain feedback loops which makes the high speed VLSI implementation easy. A modified design is also developed by using a finite signal as the input to the FEXT canceller such that the hardware complexity of the proposed FEXT canceller can be reduced.

Abstract: The present invention relates to data processing techniques in multi-channel data transmission systems. In this invention, a method to efficiently deal with FEXT is proposed and a circuit architecture to implement the proposed MIMO-THP equalizer is developed for the application of high/ultra-high speed Ethernet systems. The proposed method relies on the fact that FEXT inherently contains information about the symbols transmitted from the far end transmitters and it can be viewed as a signal rather than noise. Compared with the traditional FEXT cancellation approaches, the proposed design inherits both advantages of MIMO equalization technique and TH precoding technique, thus having better performance. Unlike the existing MIMO-THP technology, the proposed design completely removes the feedback loops in the existing MIMO-THP architecture. Therefore, pipelining techniques can be easily applied to obtain a high-speed design of a multi-channel DSP transceiver.

Abstract: A method to design low complexity and low power echo and NEXT cancellers based on wordlength reduction technique is presented. A circuit architecture to implement echo and cancellers is also presented. The low complexity and low power design relies on the fact that a TH precoder can be viewed as an IIR filter with an input equal to the sum of the original input to the TH precoder and a compensation signal. The proposed design also relies on the fact that sum of the original input to the TH precoder and the compensation signal has finite levels, which can be represented in less bits than the original input of the echo and NEXT cancellers. An improved design by exploiting the statistics of the compensation signal is also proposed to further bring down the complexity and power consumption of these cancellers.

Abstract: Various systems and methods related to equalization precoding in a communications channel are disclosed. In one implementation precoding is performed on signals transmitted over an optical channel. In one implementation precoding and decoding operations are performed in parallel to facilitate high speed processing in relatively low cost circuits. Initialization of the precoders may be realized by transmitting information related to the characteristics of the channel between transceiver pairs.

Abstract: Various systems and methods related to equalization precoding in a communications channel are disclosed. In one implementation preceding is performed on signals transmitted over an optical channel. In one implementation preceding and decoding operations are performed in parallel to facilitate high speed processing in relatively low cost circuits. Initialization of the precoders may be realized by transmitting information related to the characteristics of the channel between transceiver pairs.

Abstract: The present invention relates to design and implementation of low complexity adaptive echo and NEXT cancellers in multi-channel data transmission systems. In this invention, a highly efficient weight update scheme is proposed to reduce the computational cost of the weight update part in adaptive echo and NEXT cancellers. Based on the proposed scheme, the hardware complexity of the weight update part can be further reduced by applying the word-length reduction technique. The proposed scheme is general and suitable for real applications such as design of a low complexity transceiver in 10GBase-T. Different with prior work, this invention considers the complexity reduction in weight update part of the adaptive filters such that the overall complexity of these adaptive cancellers can be significantly reduced.

Abstract: A method to design low complexity and low power echo and NEXT cancellers based on wordlength reduction technique is presented. A circuit architecture to implement echo and cancellers is also presented. The low complexity and low power design relies on the fact that a TH precoder can be viewed as an IIR filter with an input equal to the sum of the original input to the TH precoder and a compensation signal. The proposed design also relies on the fact that sum of the original input to the TH precoder and the compensation signal has finite levels, which can be represented in less bits than the original input of the echo and NEXT cancellers. An improved design by exploiting the statistics of the compensation signal is also proposed to further bring down the complexity and power consumption of these cancellers.

Abstract: The invention relates to techniques for implementing high-speed precoders, such as Tomlinson-Harashima (TH) precoders. In one aspect of the invention, look-ahead techniques are utilized to pipeline a TH precoder, resulting in a high-speed TH precoder. These techniques may be applied to pipeline various types of TH precoders, such as Finite Impulse Response (FIR) precoders and Infinite Impulse Response (IIR) precoders. In another aspect of the invention, parallel processing multiple non-pipelined TH precoders results in a high-speed parallel TH precoder design. Utilization of high-speed TH precoders may enable network providers to for example, operate 10 Gigabit Ethernet with copper cable rather than fiber optic cable.

Abstract: A memory address generation method and circuit architecture for time-multiplexed RS-based LDPC code decoder is presented. The method is developed for non quasi-cyclic RS-based LDPC code decoder implementation. A circuit for the memory address generation method achieves low area. High throughput time-multiplexed RS-based LDPC code decoder design models and circuit architectures are presented. The decoder models are specifically developed for 10BASE-T (10-Gigabit Ethernet Transceiver Over Copper) system. These time-multiplexed architectures enable higher throughput with lower area.

Abstract: A method to design parallel TH precoders and a circuit architecture to implement parallel TH precoders have been presented. The parallel design relies on the fact that a TH precoder can be viewed as an IIR filter with an input equal to the sum of the original input to the TH precoder and a compensation signal. The parallel design also relies on the fact that the compensation signal has finite levels. Therefore, precomputation techniques can be applied to calculate intermediate signal values for all possible values of the compensation signal.

Abstract: Encoders and methods for designing encoders for Low Density Parity Check (LDPC) and other block codes are presented. An efficient and systematic method for designing partially parallel encoders is presented. A parallelism factor is selected such that the end result for the encoder is similar to the partially parallel G matrix multiplication method. In addition to the method an initial circuit is given for the G matrix multiplication encoder and the RU encoder. A circuit for the hybrid encoder is presented which achieves less power consumption and smaller area than an equivalent encoder based on the G matrix multiplication with a smaller critical path than previous encoders.

Abstract: A method to efficiently deal with FEXT crosstalk in wireline communication system via MIMO equalization is presented. A MIMO-DFE based receiver architecture is developed to demonstrate the advantage over the traditional receiver design. A MIMO structure for systems with TH precoding is also developed for 10GBASE-T application. The proposed architecture overcomes the limitation of the traditional schemes and achieves a better SNR performance and lower receiver complexity. The proposed method relies on the fact that FEXT inherently contains information about the symbols transmitted from the three far end transmitters and it can be viewed as a signal rather than noise. Therefore, MIMO techniques are applied to turn FEXT into a benefit for the receiver design.

Abstract: A K-bit information signal represented by a polynomial U(x) having a degree K?1 is received. The information signal is transformed to form a transformed information signal using a first transform represented by a polynomial G1(x) having a degree P. The transformed information signal is represented by a polynomial T(x) having a degree K+P?1. T(x) equals U(x)G1(x). An initial cyclic code represented by a polynomial R1(x) is generated for the transformed information signal using a second transform represented by a polynomial G2(x), where G2(x) has high-order leading-zero terms. R1(x) equals the remainder obtained by dividing T(x) by G2(x). The initial cyclic code is transformed to form a final cyclic code represented by a polynomial R2(x) using the first transform. R2(x) equals R1(x)/G1(x).

Abstract: A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a multiplicand (X) are processed together to generate partial products. The partial products are accumulated to generate a product (P). To compensate for the quantization error, Booth encoder outputs are used for the generation of error compensation bias. The truncated bits are divided into two groups, a major least significant bit group and a minor least significant bit group, depending upon their effects on the quantization error. Different error compensation methods are applied to each group.

Abstract: Digital circuits and methods for designing digital circuits are presented. In an embodiment, a number of bits (B) of a bit-stream to be processed in parallel by a digital circuit is selected. A clocking rate (C) is selected for the digital circuit such that a product (P), P being equal to B times C, is equal to at least 1 gigabit per second. An initial circuit capable of serially processing the bits of the bit-stream at a data processing rate less than P is formed. This initial circuit includes a feedback loop having N+1 delays. N is a whole number greater than zero. The initial circuit is unfolded by a factor of B to form B parallel processing pipelines for the bits of the bit-stream. An N-step look-ahead network is formed to provide inputs to the B parallel processing pipelines. The unfolded circuit is retimed to achieve the selected clocking rate (C).

Abstract: Digital circuits and methods for designing digital circuits are presented. More particularly, the present invention relates to error correction circuits and methods in communications and other systems. In the present invention, a novel K-nested layered look-ahead method and its corresponding architecture, which combine K-trellis steps into one trellis step (where K is the encoder constraint length), are proposed for implementing low-latency high-throughput rate Viterbi decoder circuits. The main idea of the present invention involves combining K-trellis steps as a pipeline structure and then combining the resulting look-ahead branch metrics as a tree structure in a layered manner to decrease the ACS precomputation latency of look-ahead Viterbi decoder circuits. The proposed method guarantees parallel paths between any two trellis states in the look-ahead trellises and distributes the add-compare-select (ACS) computations to all trellis layers.