Abstract: An n-level look-ahead network converts input values to intermediate values that are provided to a plurality of multiplexers arranged to form a pipelined multiplexer loop. The first stage of the multiplexer loop consists of a single multiplexer. The second stage consists of at least two multiplexers. Communication links couple the output ports of the second stage multiplexers to the input ports of the first stage multiplexer. A first feedback loop electrically couples the output port of the first stage multiplexer to the control port of the first stage multiplexer. This first feedback loop has a first delay device having a first delay time. A second feedback loop couples the output port of the first stage multiplexer to the control ports of the second stage multiplexers. This second feedback loop includes the first delay device and a second delay device having a second delay time.

Abstract: Turbo decoders may have large decoding latency and low throughput due to iterative decoding. One way to increase the throughput and reduce the latency of turbo decoders is to use high speed decoding schemes. In particular, area-efficient parallel decoding schemes may be used to overcome the decoding latency and throughput associated with turbo decoders. In addition, hybrid parallel decoding schemes may be used in high-level parallelism implementations. Moreover, the area-efficient parallel decoding schemes introduce little or no performance degradation.

Abstract: A joint code-encoder-decoder design approach and circuit architecture design for (3,k)-regular LDPC coding system implementation. The joint design process relies on a high girth (2,k)-regular LDPC code construction. The decoder realizes partly parallel decoding. The encoding scheme only contains multiplications between sparse matrices and vector and multiplication between a very small dense matrix and vector.

Abstract: An error compensation bias circuit and method for a canonic signed digit (CSD) fixed-width multiplier that receives a W-bit input and produces a W-bit product. Truncated bits of the multiplier are divided into two groups (a major group and a minor group) depending upon their effects on quantization error. An error compensation bias is expressed in terms of the truncated bits in the major group. The effects of the remaining truncated bits in the minor group are taken into account by a probabilistic estimation. The error compensation bias circuit typically requires only a few logic gates to implement.

Abstract: Digital communications devices having high-speed add-compare-select circuits, and methods for designing the same. The add-compare-select circuits include logic segments separated by delay devices. The separation of the logic segments allows for pipelining of the add-compare-select processes and advantageous circuit retiming. The pipelining and advantageous circuit retiming permit the digital communications devices to be clocked at higher rates than similar digital communications devices having conventional add-compare-select circuits.

Abstract: A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a multiplicand (X) are processed together to generate partial products. The partial products are accumulated to generate a product (P). To compensate for the quantization error, Booth encoder outputs are used for the generation of error compensation bias. The truncated bits are divided into two groups, a major least significant bit group and a minor least significant bit group, depending upon their effects on the quantization error. Different error compensation methods are applied to each group.

Abstract: A fast, scalable, systolic modular multiplier is presented. Linear throughput scalability with respect to consumed hardware resources is achieved through simultaneous parallel processing of multiple independent data streams. Optimal clock rates are attained by virtue of systolic properties of limited fan-out of all signal paths and nearest neighbor interconnections. Signal sharing among input and output busses and a common control interface for all independent data streams is made possible, thus benefiting integrated circuit implementations.

Abstract: A K-bit information signal represented by a polynomial U(x) having a degree K?1 is received. The information signal is transformed to form a transformed information signal using a first transform represented by a polynomial G1(x) having a degree P. The transformed information signal is represented by a polynomial T(x) having a degree K+P?1. T(x) equals U(x)G1(x). An initial cyclic code represented by a polynomial R1(x) is generated for the transformed information signal using a second transform represented by a polynomial G2(x), where G2(x) has high-order leading-zero terms. R1(x) equals the remainder obtained by dividing T(x) by G2(x). The initial cyclic code is transformed to form a final cyclic code represented by a polynomial R2(x) using the first transform. R2(x) equals R1(x)/G1(x).

Abstract: Digital communications devices having high-speed add-compare-select circuits, and methods for designing the same. The add-compare-select circuits include logic segments separated by delay devices. The separation of the logic segments allows for pipelining of the add-compare-select processes and advantageous circuit retiming. The pipelining and advantageous circuit retiming permit the digital communications devices to be clocked at higher rates than similar digital communications devices having conventional add-compare-select circuits.

Abstract: A joint code-encoder-decoder design approach and circuit architecture design for (3,k)-regular LDPC coding system implementation. The joint design process relies on a high girth (2,k)-regular LDPC code construction. The decoder realizes partly parallel decoding. The encoding scheme only contains multiplications between sparse matrices and vector and multiplication between a very small dense matrix and vector.

Abstract: A fast, scalable, systolic modular multiplier is presented. Linear throughput scalability with respect to consumed hardware resources is achieved through simultaneous parallel processing of multiple independent data streams. Optimal clock rates are attained by virtue of systolic properties of limited fan-out of all signal paths and nearest neighbor interconnections. Signal sharing among input and output busses and a common control interface for all independent data streams is made possible, thus benefiting integrated circuit implementations.

Abstract: A fast, scalable, systolic modular multiplier based on functional array partitioning and high-radix modular reduction is presented. Systolic paradigms of limited fan-out on all signal paths and nearest neighbor interconnections guarantee optimally fast clock rates. Linear throughput scalability with respect to consumed hardware resources is achieved through simultaneous parallel processing of multiple independent data streams. Signal sharing among input and output busses and a common control interface for all independent data streams is made possible, thus benefiting integrated circuit implementations. Reductions in number of delay registers and required number of independent data streams for a given throughput requirement are achieved when interconnection delay does not dominate over processing element delay.

Abstract: An error compensation bias circuit and method for a canonic signed digit (CSD) fixed-width multiplier that receives a W-bit input and produces a W-bit product. Truncated bits of the multiplier are divided into two groups (a major group and a minor group) depending upon their effects on quantization error. An error compensation bias is expressed in terms of the truncated bits in the major group. The effects of the remaining truncated bits in the minor group are taken into account by a probabilistic estimation. The error compensation bias circuit typically requires only a few logic gates to implement.

Abstract: A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a multiplicand (X) are processed together to generate partial products. The partial products are accumulated to generate a product (P). To compensate for the quantization error, Booth encoder outputs are used for the generation of error compensation bias. The truncated bits are divided into two groups, a major least significant bit group and a minor least significant bit group, depending upon their effects on the quantization error. Different error compensation methods are applied to each group.

Abstract: A K-bit information signal represented by a polynomial U(x) having a degree K−1 is received. The information signal is transformed to form a transformed information signal using a first transform represented by a polynomial G1(x) having a degree P. The transformed information signal is represented by a polynomial T(x) having a degree K+P−1. T(x) equals U(x)G1(x). An initial cyclic code represented by a polynomial R1(x) is generated for the transformed information signal using a second transform represented by a polynomial G2(x), where G2(x) has high-order leading-zero terms. R1(x) equals the remainder obtained by dividing T(x) by G2(x). The initial cyclic code is transformed to form a final cyclic code represented by a polynomial R2(x) using the first transform. R2(x) equals R1(x)/G1(x).

Abstract: An n-level look-ahead network converts input values to intermediate values that are provided to a plurality of multiplexers arranged to form a pipelined multiplexer loop. The first stage of the multiplexer loop consists of a single multiplexer. The second stage consists of at least two multiplexers. Communication links couple the output ports of the second stage multiplexers to the input ports of the first stage multiplexer. A first feedback loop electrically couples the output port of the first stage multiplexer to the control port of the first stage multiplexer. This first feedback loop has a first delay device having a first delay time. A second feedback loop couples the output port of the first stage multiplexer to the control ports of the second stage multiplexers. This second feedback loop includes the first delay device and a second delay device having a second delay time.

Abstract: Digital circuits and methods for designing digital circuits are presented. In an embodiment, a number of bits (B) of a bit-stream to be processed in parallel by a digital circuit is selected. A clocking rate (C) is selected for the digital circuit such that a product (P), P being equal to B times C, is equal to at least 1 gigabit per second. An initial circuit capable of serially processing the bits of the bit-stream at a data processing rate less than P is formed. This initial circuit includes a feedback loop having N+1 delays. N is a whole number greater than zero. The initial circuit is unfolded by a factor of B to form B parallel processing pipelines for the bits of the bit-stream. An N-step look-ahead network is formed to provide inputs to the B parallel processing pipelines. The unfolded circuit is retimed to achieve the selected clocking rate (C).

Abstract: Turbo decoders may have large decoding latency and low throughput due to iterative decoding. One way to increase the throughput and reduce the latency of turbo decoders is to use high speed decoding schemes. In particular, area-efficient parallel decoding schemes may be used to overcome the decoding latency and throughput associated with turbo decoders. In addition, hybrid parallel decoding schemes may be used in high-level parallelism implementations. Moreover, the area-efficient parallel decoding schemes introduce little or no performance degradation.

Abstract: Various systems and methods related to equalization precoding in a communications channel are disclosed. In one implementation preceding is performed on signals transmitted over an optical channel. In one implementation preceding and decoding operations are performed in parallel to facilitate high speed processing in relatively low cost circuits. Initialization of the precoders may be realized by transmitting information related to the characteristics of the channel between transceiver pairs.

Abstract: A serial Huffman decoder that is concise and capable of extremely high rates of operation is described. Optimal speed is attained because the critical-path of an embodying circuit has only a memory in the critical path. No other functions or operations are entailed. This being the only unequivocally essential device in the implementation of a mapping such as Huffman, the critical path is blatantly optimal. The codetable, composed of a specially modified Huffman binary tree, is much more compact than the typical Huffman binary tree.