Patents by Inventor Keum-Bum Lee
Keum-Bum Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220359400Abstract: Embodiments of the present invention provide a semiconductor device capable of reducing parasitic capacitance between neighboring conductive lines and a method for fabricating the same. According to an embodiment of the present invention, a semiconductor device comprises: a conductive line formed over a substrate; and a multi-layered spacer covering both sidewalls of the conductive line, wherein the multi-layered spacer is stacked in the order of a diffusion barrier material, boron nitride layer, and an antioxidant material.Type: ApplicationFiled: October 22, 2021Publication date: November 10, 2022Inventors: Jin Yul LEE, Beom Ho Mun, Seung Woo Jin, Keum Bum Lee
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Patent number: 9972384Abstract: An electronic device comprising a semiconductor memory unit that includes a resistance variable element formed over a substrate, and including stacked therein a bottom electrode, a variable resistance layer and a top electrode, and a barrier layer formed over the resistance variable element, and including an amorphous silicon layer which is doped with at least one kind of impurity.Type: GrantFiled: April 14, 2017Date of Patent: May 15, 2018Assignee: SK hynix Inc.Inventors: Sook-Joo Kim, Jae-Geun Oh, Keum-Bum Lee, Hyung-Suk Lee
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Publication number: 20170221557Abstract: An electronic device comprising a semiconductor memory unit that includes a resistance variable element formed over a substrate, and including stacked therein a bottom electrode, a variable resistance layer and a top electrode, and a barrier layer formed over the resistance variable element, and including an amorphous silicon layer which is doped with at least one kind of impurity.Type: ApplicationFiled: April 14, 2017Publication date: August 3, 2017Inventors: Sook-Joo Kim, Jae-Geun Oh, Keum-Bum Lee, Hyung-Suk Lee
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Patent number: 9627616Abstract: An electronic device comprising a semiconductor memory unit that includes a resistance variable element formed over a substrate, and including stacked therein a bottom electrode, a variable resistance layer and a top electrode, and a barrier layer formed over the resistance variable element, and including an amorphous silicon layer which is doped with at least one kind of impurity.Type: GrantFiled: March 25, 2014Date of Patent: April 18, 2017Assignee: SK hynix Inc.Inventors: Sook-Joo Kim, Jae-Geun Oh, Keum-Bum Lee, Hyung-Suk Lee
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Patent number: 9406871Abstract: According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.Type: GrantFiled: July 23, 2015Date of Patent: August 2, 2016Assignees: KABUSHIKI KAISHA TOSHIBA, SK HYNIX INC.Inventors: Masahiko Nakayama, Masatoshi Yoshikawa, Tadashi Kai, Yutaka Hashimoto, Masaru Toko, Hiroaki Yoda, Jae Geun Oh, Keum Bum Lee, Choon Kun Ryu, Hyung Suk Lee, Sook Joo Kim
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Patent number: 9305775Abstract: An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer.Type: GrantFiled: March 25, 2015Date of Patent: April 5, 2016Assignee: SK Hynix Inc.Inventors: Young Ho Lee, Keum Bum Lee, Min Yong Lee, Hyung Suk Lee, Seung Beom Baek
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Publication number: 20150325785Abstract: According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.Type: ApplicationFiled: July 23, 2015Publication date: November 12, 2015Inventors: Masahiko NAKAYAMA, Masatoshi YOSHIKAWA, Tadashi KAI, Yutaka HASHIMOTO, Masaru TOKO, Hiroaki YODA, Jae Geun OH, Keum Bum LEE, Choon Kun RYU, Hyung Suk LEE, Sook Joo KIM
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Patent number: 9123879Abstract: According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.Type: GrantFiled: March 10, 2014Date of Patent: September 1, 2015Inventors: Masahiko Nakayama, Masatoshi Yoshikawa, Tadashi Kai, Yutaka Hashimoto, Masaru Toko, Hiroaki Yoda, Jae Geun Oh, Keum Bum Lee, Choon Kun Ryu, Hyung Suk Lee, Sook Joo Kim
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Publication number: 20150200088Abstract: An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer.Type: ApplicationFiled: March 25, 2015Publication date: July 16, 2015Inventors: Young Ho LEE, Keum Bum LEE, Min Yong LEE, Hyung Suk LEE, Seung Beom BAEK
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Patent number: 9018612Abstract: An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer.Type: GrantFiled: December 13, 2012Date of Patent: April 28, 2015Assignee: SK Hynix Inc.Inventors: Young Ho Lee, Keum Bum Lee, Min Young Lee, Hyung Suk Lee, Seung Beom Baek
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Publication number: 20150069557Abstract: According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.Type: ApplicationFiled: March 10, 2014Publication date: March 12, 2015Inventors: Masahiko NAKAYAMA, Masatoshi YOSHIKAWA, Tadashi KAI, Yutaka HASHIMOTO, Masaru TOKO, Hiroaki YODA, Jae Geun OH, Keum Bum LEE, Choon Kun RYU, Hyung Suk LEE, Sook Joo KIM
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Publication number: 20140287535Abstract: An electronic device comprising a semiconductor memory unit that includes a resistance variable element formed over a substrate, and including stacked therein a bottom electrode, a variable resistance layer and a top electrode, and a barrier layer formed over the resistance variable element, and including an amorphous silicon layer which is doped with at least one kind of impurity.Type: ApplicationFiled: March 25, 2014Publication date: September 25, 2014Applicant: SK HYNIX INC.Inventors: Sook-Joo Kim, Jae-Geun Oh, Keum-Bum Lee, Hyung-Suk Lee
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Publication number: 20140054532Abstract: An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer.Type: ApplicationFiled: December 13, 2012Publication date: February 27, 2014Applicant: SK HYNIX INC.Inventors: Young Ho LEE, Keum Bum LEE, Min Yong LEE, Hyung Suk LEE, Seung Beom BAEK
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Patent number: 8609503Abstract: The manufacturing of a phase change memory device that includes a switching device, a bottom electrode contact in contact with the switching device and a porous spacer formed on the bottom electrode contact. The formed bottom electrode contact exposes a switching device on a semiconductor substrate which the switching device is formed in, forming an insulating layer on a resultant structure of the semiconductor substrate including the bottom electrode contact by using an insulating compound having materials with different atomic sizes, and forming an insulating spacer within the bottom electrode contact hole by selectively etching the insulating layer.Type: GrantFiled: January 25, 2012Date of Patent: December 17, 2013Assignee: Hynix Semiconductor Inc.Inventors: Keum Bum Lee, Su Jin Chae, Hye Jin Seo
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Patent number: 8546177Abstract: Methods of manufacturing a phase-change memory device and a semiconductor device are provided. The method of manufacturing the phase-change memory device includes forming a switching device layer, an ohmic contact layer, and a hard mask layer on a semiconductor substrate, patterning the hard mask layer to form a hard mask pattern, etching the ohmic layer and the switching layer using the hard mask pattern to form a pattern structure including an ohmic contact pattern, a switching device pattern, and the hard mask pattern, selectively oxidizing a surface of the pattern structure, forming an insulating layer to bury the pattern structure, and selectively removing the hard mask pattern other than the oxidized surface thereof to form a contact hole.Type: GrantFiled: December 29, 2011Date of Patent: October 1, 2013Assignee: Hynix Semiconductor Inc.Inventors: Hye Jin Seo, Keum Bum Lee
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Publication number: 20130102120Abstract: Methods of manufacturing a phase-change memory device and a semiconductor device are provided. The method of manufacturing the phase-change memory device includes forming a switching device layer, an ohmic contact layer, and a hard mask layer on a semiconductor substrate, patterning the hard mask layer to form a hard mask pattern, etching the ohmic layer and the switching layer using the hard mask pattern to form a pattern structure including an ohmic contact pattern, a switching device pattern, and the hard mask pattern, selectively oxidizing a surface of the pattern structure, forming an insulating layer to bury the pattern structure, and selectively removing the hard mask pattern other than the oxidized surface thereof to form a contact hole.Type: ApplicationFiled: December 29, 2011Publication date: April 25, 2013Inventors: Hye Jin Seo, Keum Bum Lee
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Publication number: 20120156851Abstract: A phase change memory device is provided that includes a switching device, a bottom electrode contact in contact with the switching device and a porous spacer formed on the bottom electrode contact.Type: ApplicationFiled: January 25, 2012Publication date: June 21, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Keum Bum LEE, Su Jin CHAE, Hye Jin SEO
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Patent number: 8049199Abstract: A phase change memory device and a method for manufacturing the same. The method includes the steps of defining bottom electrode contact holes by removing portions of an insulation layer, to expose bottom electrodes, on a semiconductor substrate on which the bottom electrodes and the insulation layer are sequentially formed; forming amorphous silicon spacers on inner sidewalls of the bottom electrode contact holes; and forming bottom electrode contacts in the bottom electrode contact holes.Type: GrantFiled: July 8, 2008Date of Patent: November 1, 2011Assignee: Hynix Semiconductor Inc.Inventors: Yong Seok Eun, Su Jin Chae, Keum-Bum Lee, Heon-Yong Chang, Min-Yong Lee
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Publication number: 20110073826Abstract: A phase change memory device is provided that includes a switching device, a bottom electrode contact in contact with the switching device and a porous spacer formed on the bottom electrode contact.Type: ApplicationFiled: December 29, 2009Publication date: March 31, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Keum Bum LEE, Su Jin CHAE, Hye Jin SEO
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Patent number: 7893421Abstract: A phase change memory device is presented that has a lower electrode contact that has a gradient resistance profile ranging from a lower resistive lower end to a higher resistive upper end. The phase change memory device includes a semiconductor substrate, a lower electrode contact, and a phase change pattern. The semiconductor substrate has a switching device. The lower electrode contact is formed on the switching device and has a specific resistance which gradually increases from a lower part to an upper part of the lower electrode contact. The phase change pattern layer is formed on the lower electrode contact.Type: GrantFiled: June 11, 2009Date of Patent: February 22, 2011Assignee: Hynix Semiconductor Inc.Inventors: Keum Bum Lee, Hye Jin Seo, Hyung Suk Lee