Abstract: A phase-change memory device and a fabrication method thereof, capable of reducing driving current while minimizing a size of a contact hole used for forming a PN diode in the phase-change memory device that employs the PN diode. The method of fabricating the phase-change memory device includes the steps of preparing a semiconductor substrate having a junction area formed with a dielectric layer, forming an interlayer dielectric layer having etching selectivity lower than that of the dielectric layer over an entire structure, and forming a contact hole by removing predetermined portions of the interlayer dielectric layer and the dielectric layer. The contact area between the PN diode and the semiconductor substrate is increased so that interfacial resistance is reduced.

Abstract: A method of manufacturing a memory device and a phase-change memory device is presented. The method of manufacturing the memory device includes performing Ge ion implantation on a top surface of a first layer. The method also includes performing a fast heat treatment on the ion-implanted first layer. The method also includes forming a second layer on a top of the fast heat-treated first layer.

Abstract: A phase-change random access memory (PRAM) is presented which can ensure the integrity of the electrical characteristics of driving transistors even when the PRAM is with a high temperature SEG fabrication process because the fabrication time is minimized. A method of manufacturing the PRAM includes the following steps. After preparing a semiconductor substrate having a cell area and a peripheral area, a junction area is formed in the cell area. Then, a transistor having a gate electrode with a single conductive layer is formed in the peripheral area. Subsequently, a first interlayer dielectric layer is formed at an upper portion of the semiconductor substrate, and then a contact hole is formed by etching the first interlayer dielectric layer to expose a predetermined portion of the junction area. Next, an epitaxial layer is grown in the contact hole.

Abstract: A phase change memory device is presented that has a lower electrode contact that has a gradient resistance profile ranging from a lower resistive lower end to a higher resistive upper end. The phase change memory device includes a semiconductor substrate, a lower electrode contact, and a phase change pattern. The semiconductor substrate has a switching device. The lower electrode contact is formed on the switching device and has a specific resistance which gradually increases from a lower part to an upper part of the lower electrode contact. The phase change pattern layer is formed on the lower electrode contact.

Abstract: A phase change memory device includes a semiconductor substrate, a first conductive pattern formed on the semiconductor substrate, a second conductive pattern contacting an upper surface of the first conductive pattern and having a diameter less than a diameter of the first conductive pattern, and a phase change material layer contacting the second conductive pattern.

Abstract: A phase change memory device and a method for manufacturing the same. The method includes the steps of defining bottom electrode contact holes by removing portions of an insulation layer, to expose bottom electrodes, on a semiconductor substrate on which the bottom electrodes and the insulation layer are sequentially formed; forming amorphous silicon spacers on inner sidewalls of the bottom electrode contact holes; and forming bottom electrode contacts in the bottom electrode contact holes.

Abstract: A phase-change memory device and a fabrication method thereof, capable of reducing driving current while minimizing a size of a contact hole used for forming a PN diode in the phase-change memory device that employs the PN diode. The method of fabricating the phase-change memory device includes the steps of preparing a semiconductor substrate having a junction area formed with a dielectric layer, forming an interlayer dielectric layer having etching selectivity lower than that of the dielectric layer over an entire structure, and forming a contact hole by removing predetermined portions of the interlayer dielectric layer and the dielectric layer. The contact area between the PN diode and the semiconductor substrate is increased so that interfacial resistance is reduced.

Abstract: A method for fabricating a trench dielectric layer in a semiconductor device is provided. A trench is formed in a semiconductor substrate and a liner nitride layer is then formed on an inner wall of the trench. A liner oxide layer formed on the liner nitride layer is nitrified in order to protect the liner nitride layer from being exposed. Subsequently, the trench is filled with one or more dielectric layers.

Abstract: Disclosed herein is a method of fabricating a semiconductor device having a metal fuse. The method includes forming a plate electrode on a semiconductor substrate, forming an interlayer insulating layer on the plate electrode, forming a barrier metal layer containing either silicon or aluminum, a first metal layer and an antireflection layer containing either silicon or aluminum sequentially from bottom to top on the interlayer insulating layer. The method also includes patterning the antireflection layer, the first metal layer, and the barrier metal layer to form a first metal interconnection. The method also includes forming a fuse with the same material and structure as those of the first metal interconnection while forming the first metal interconnection.

Abstract: A method for forming a capacitor includes forming a concave mold over a semiconductor substrate. A storage node is formed on the concave mold. A dielectric layer including a zirconium oxide (ZrO2) layer is deposited over the storage node at a first temperature. A radical pile-up treatment on the dielectric layer is performed in an atmosphere including radicals at a second temperature higher than the first temperature to induce crystallization of the dielectric layer. A plate node is formed over the dielectric layer.