Patents by Inventor Keun Do Ban

Keun Do Ban has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7314853
    Abstract: Disclosed herein are photoresist cleaning solutions useful for cleaning a semiconductor substrate in the last step of a developing step when photoresist patterns are formed. Also disclosed herein are methods for forming photoresist patterns using the solutions. The cleaning solutions of the present invention include H2O as a primary component, a surfactant as an additive, and optionally an alcohol compound. The cleaning solution of the present invention has lower surface tension than that of distilled water which has been used for conventional cleaning solutions, thereby improving resistance to pattern collapse and stabilizing the photoresist pattern formation.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: January 1, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventors: Geun Su Lee, Sam Young Kim, Keun Do Ban
  • Publication number: 20070161221
    Abstract: A method for manufacturing a semiconductor device includes forming a second storage node contact hole with a mask for storage node and securing an overlay margin between a storage node contact hole and a storage node with a hard mask layer that serves as a hard mask as well as an anti-reflection film to reduce contact resistance, prevent reduction of a line-width of a lower interlayer insulating film and eliminate processes for depositing the interlayer insulating film and a polysilicon layer and etching the polysilicon layer to reduce a production period and cost of products.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 12, 2007
    Applicant: Hynix Semiconductor Inc.
    Inventors: Ki Lyoung Lee, Keun Do Ban, Sa Ro Han Park
  • Patent number: 7123362
    Abstract: A method for aligning wafer includes selecting a nun-defective wafer alignment mark of a first wafer loaded in an exposure apparatus, and storing non-defective wafer alignment marks as a gray level reference image. A plurality of wafer alignment marks of a loaded second wafer are stored. Each of the plurality of wafer alignment mark images of the second wafer are respectively compared with the reference image of the first wafer pixel by pixel to obtain matching value for each of the plurality of the wafer alignment mark images. Each of the plurality of values of the matching values are compared with a set minimum value. The wafer alignment mark image having the matching value smaller than the minimum value with the reference image is replaced. The alignment information for an underlying layer using a wafer alignment information for an underlying layer using a wafer alignment sensor is obtained.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: October 17, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventor: Keun Do Ban