Patents by Inventor Keun-ho CHOI

Keun-ho CHOI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140021608
    Abstract: A semiconductor package includes a first semiconductor chip including a first chip pad located on an upper surface thereof, a second semiconductor chip offset-stacked on the upper surface of the first semiconductor chip and including a second chip pad located on an upper surface thereof, a chip coupling ball located on a first board pad of the first semiconductor chip, a chip coupling bump located on a second board pad of the second semiconductor chip, and a chip connection wire connecting the chip coupling ball and the chip coupling bump. The chip connection wire has a chip connection curve part with a reverse curve shape.
    Type: Application
    Filed: May 6, 2013
    Publication date: January 23, 2014
    Applicant: Samsunung Electronics., Ltd.
    Inventor: KEUN-HO CHOI
  • Publication number: 20140008796
    Abstract: A semiconductor package includes a mounting board including a bonding pad, first and second semiconductor chips sequentially stacked on the mounting board, a first wire connecting a first region of the bonding pad to a chip pad of the first semiconductor chip, and a second wire connecting the first region of the bonding pad to a chip pad of the second semiconductor chip, the second wire having a reverse loop configuration.
    Type: Application
    Filed: July 3, 2013
    Publication date: January 9, 2014
    Inventor: Keun-Ho CHOI
  • Publication number: 20100314740
    Abstract: A multi-chip package device can include a plurality of integrated circuit device chips stacked on one another inside a multi-chip package including the device. The device can include an electrically isolated multi-chip support structure that is directly connected to first and second electrically active integrated circuit structures via respective first and second adhesive layers located on opposing sides of the electrically isolated multi-chip support structure.
    Type: Application
    Filed: May 10, 2010
    Publication date: December 16, 2010
    Inventors: Keun-ho CHOI, Myung-kee CHUNG, Kun-dae YEOM, Kil-soo KIM