Abstract: Fence randomization with inter-chip fencing constraints, including: receiving a fencing setup comprising one or more parameters for fencing a plurality of chips in a plurality of drawers; and selecting, based on the one or more parameters and one or more dependencies for implementing the one or more parameters, a subset of the plurality of chips for fencing, wherein the subset of the plurality of chips are selected at least partially randomly; generating a testing configuration indicating the selected subset of the plurality of chips.

Abstract: Embodiments of the present disclosure generally relate to augmented reality waveguide combiners. The waveguides includes a waveguide substrate, having a substrate refractive index (RI) nsub, a slab waveguide layer disposed over the waveguide substrate, the slab waveguide layer having a slab RI nswg and a slab depth dswg, the slab depth dswg from a lower surface to an upper surface of the slab waveguide layer, at least one grating defined by a plurality of grating structures, the grating structures are disposed in, on, or over the slab waveguide layer, and a superstrate between and over the grating structures, the superstrate having a superstrate RI nsuperstrate and an interface with the slab waveguide layer. The slab RI nswg is greater than the substrate RI nsub and the slab RI nswg is greater than the superstrate RI nsuperstrate.

Abstract: Disclosed herein are compounds of formula I: or a pharmaceutically acceptable salt thereof, where the variables are as defined herein. These compounds are useful in treating RET associated cancers. Formulations containing the compounds of formula I and methods of making the compounds of formula I are also disclosed.

Abstract: In one aspect, a leveling assembly for adjusting the levelness or skew angle of a bottom rail of a covering for an architectural structure includes at least one movable or slideable component configured to be moved or slid laterally relative to the bottom rail or a headrail of the covering to adjust the length(s) along which one or more of the lift cords extend within the bottom rail or headrail, which, in turn, adjusts the effective length of such lift cord(s) defined between the bottom rail and the headrail of the covering. Such adjustment of the effective length(s) of the lift cord(s) results in the horizontal orientation or skew angle of the bottom rail being varied, thereby allowing the levelness of the bottom rail to be adjusted, as desired.

Abstract: Embodiments of the present disclosure generally relate to methods for forming a waveguide. Methods may include measuring a waveguide substrate, the waveguide having a substrate thickness distribution; and depositing an index-matched layer onto a surface of the waveguide, the index-matched layer having a first surface disposed on the waveguide substrate and a second surface opposing the first surface, wherein the index-matched layer is disposed only over a portion of the waveguide substrate, and a device slope of a second surface of the index-matched layer is substantially the same as the waveguide slope of the first surface of the waveguide.

Abstract: Disclosed herein are novel lipids that can be used in combination with other lipid components, such as helper lipids, structural lipids, and cholesterols, to form lipid nanoparticles for delivery of therapeutic agents, such as nucleic acids (e.g., circular polynucleotides), both in vitro and in vivo.

Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon FET. A ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. A gate can then be grown on the ferroelectric layer.

Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers, such as undoped semiconductor layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be preferentially etched away, leaving the doped semiconductor layers as fins for a ribbon FET. In another embodiment, an interlayer can be deposited on top of a semiconductor layer, and a ferroelectric layer can be deposited on the interlayer. The interlayer can bridge a gap in lattice parameters between the semiconductor layer and the ferroelectric layer.

Abstract: Technologies for a transistor with a thin-film ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a thin layer of scandium aluminum nitride (ScxAl1-xN) ferroelectric gate dielectric. The channel of the transistor may be, e.g., gallium nitride or molybdenum disulfide. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one-transistor memory cell.

Abstract: A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and the

Abstract: In one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the FE material. The FE material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.

Abstract: In one embodiment, a transistor device includes a gate material layer on a substrate, a ferroelectric (FE) material layer on the gate material, a semiconductor channel material layer on the FE material layer, a first source/drain material on the FE material layer and adjacent the semiconductor channel material layer, and a second source/drain material on the FE material layer and adjacent the semiconductor channel material layer and on an opposite side of the semiconductor channel material layer from the first source/drain material. A first portion of the FE material layer is directly between the gate material and the first source/drain material, and a second portion of the FE material layer is directly between the gate material and the second source/drain material.

Abstract: In accordance with a designation of a private alias endpoint as a routing target for traffic directed to a service from within an isolated virtual network of a provider network, a tunneling intermediary receives a baseline packet generated at a compute instance. The baseline packet indicates a public IP (Internet Protocol) address of the service as the destination, and a private IP address of the compute instance as the source. In accordance with a tunneling protocol, the tunneling intermediary generates an encapsulation packet comprising at least a portion of the baseline packet and a header indicating the isolated virtual network. The encapsulation packet is transmitted to a node of the service.

Abstract: A valve diaphragm for a relief valve may include: a body having a first beaded end and a second beaded end, the first beaded end having a bottom surface and a bulge extending from the bottom surface. The bottom surface may be configured to contact a first portion of a corner of a lower valve body, and the bulge is configured to contact a step of an upper valve body, and the engagements of the bottom surface, the first portion of the corner, the bulge, and the step may be configured to create a fluid tight seal between the upper valve body and the lower valve body.

Abstract: Methods for extracting materials from oil seeds are disclosed. An example method may include extracting a material from an oil seed with an extraction solution to form a mixture. The extraction solution may be free of an organic solvent. The method may also include filtering the mixture into a retentate and a permeate. The method may also include drying the retentate.

Abstract: Topological superconductor devices with gates formed in two gate layers are described. A topological superconductor device includes a superconducting wire having a first junction near a first end of the superconducting wire and a second junction near a second end, opposite to the first end. The topological superconductor device further includes: (1) a first side-plunger gate and a second-side plunger gate formed in a first gate layer of the topological superconductor device, (2) a middle-plunger gate formed in the first gate layer of the topological superconductor device, (3) a first cutter gate formed in a second layer, different from the first layer, of the topological superconductor device, and (4) a second cutter gate formed in the second layer of the topological superconductor device. The plunger gates are operable to tune respective sections of the superconducting wire and the cutter gates are operable to open and close the respective junctions.

Abstract: A system may use sensor data from a facility to generate tentative values associated with an event, such as the identification of an item removed from a shelf of the facility. A confidence value associated with each of the tentative values may be less than a confidence threshold. In response, inquiry data seeking confirmation of a tentative value from an associate is generated and sent to one or more associates in the facility. Responses from the associates are collected to determine a selection of one of the tentative values. The selected tentative value is designated as output data for the system. Thereafter, the output data and the original sensor data are designated as training data, which can then be used to train or update machine learning systems. Subsequent use of the updated machine learning systems can yield more accurate results.

Abstract: This disclosure describes techniques for utilizing sensor data to automatically determine the results of events within a system. Upon receiving sensor data indicative of an event, the techniques may analyze the sensor data to determine a result of the event, such as that a particular user associated with a user identifier selected a particular item associated with an item identifier. Contents of a virtual shopping cart of the user may be maintained based on this automated analysis of sensor data. In some instances, when a confidence level associated with a result is less than a threshold, the sensor data may be sent to a client computing device for analysis by a human user. Further, when the result of an event changes from a first result to a second result, other events already processed may be reprocessed to ensure accuracy of the results.

Abstract: An integrated circuit die includes a silicon chromium (SiCr) thin film resistor disposed on a first oxide layer. The SiCr thin film resistor has a resistor body and a resistor head. A second oxide layer overlays the SiCr thin film resistor. The second oxide layer has an opening exposing a surface of the resistor head. A metal pad is disposed in the opening in the second oxide layer and is contact with the surface of the resistor head exposed by the opening. Further, an interlevel dielectric layer is disposed on the second oxide layer overlaying the SiCr thin film resistor. A metal-filled via extends from a top surface of interlevel dielectric layer through the interlevel dielectric layer and contacts the metal pad disposed in the opening in the second oxide layer.