Patents by Inventor Kevin Anglin

Kevin Anglin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11053580
    Abstract: A method includes providing a substrate, where the substrate has a patterned substrate surface, wherein the patterned substrate surface comprises a first surface region and a second surface region. The method may also include directing a depositing species to the patterned substrate surface; and directing angled ions to the patterned substrate surface, wherein the depositing species forms a deposit on the first surface region and does not form a deposit on the second surface region.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: July 6, 2021
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Kevin Anglin, Maureen Petterson
  • Patent number: 11037758
    Abstract: Provided herein are approaches for in-situ plasma cleaning of ion beam optics. In one approach, a system includes a component (e.g., a beam-line component) of an ion implanter processing chamber. The system further includes a power supply for supplying a first voltage and first current to the component during a processing mode and a second voltage and second current to the component during a cleaning mode. The second voltage and current are applied to one or more conductive beam optics of the component, individually, to selectively generate plasma around one or more of the one or more conductive beam optics. The system may further include a flow controller for adjusting an injection rate of an etchant gas supplied to the beam-line component, and a vacuum pump for adjusting pressure of an environment of the beam-line component.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: June 15, 2021
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Kevin Anglin, William Davis Lee, Peter Kurunczi, Ryan Downey, Jay T. Scheuer, Alexandre Likhanskii, William M. Holber
  • Publication number: 20210013001
    Abstract: Provided herein are approaches for in-situ plasma cleaning of ion beam optics. In one approach, a system includes a component (e.g., a beam-line component) of an ion implanter processing chamber. The system further includes a power supply for supplying a first voltage and first current to the component during a processing mode and a second voltage and second current to the component during a cleaning mode. The second voltage and current are applied to one or more conductive beam optics of the component, individually, to selectively generate plasma around one or more of the one or more conductive beam optics. The system may further include a flow controller for adjusting an injection rate of an etchant gas supplied to the beam-line component, and a vacuum pump for adjusting pressure of an environment of the beam-line component.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Kevin Anglin, William Davis Lee, Peter Kurunczi, Ryan Downey, Jay T. Scheuer, Alexandre Likhanskii, William M. Holber
  • Patent number: 10879055
    Abstract: A method is provided. The method may include providing a substrate, the substrate comprising a substrate surface, the substrate surface having a three-dimensional shape. The method may further include directing a depositing species from a deposition source to the substrate surface, wherein a layer is deposited on a deposition region of the substrate surface. The method may include performing a substrate scan during the directing or after the directing to transport the substrate from a first position to a second position. The method may also include directing angled ions to the substrate surface, in a presence of the layer, wherein the layer is sputter-etched from a first portion of the deposition region, and wherein the layer remains in a second portion of the deposition region.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: December 29, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Christopher Hatem, Kevin Anglin
  • Patent number: 10847372
    Abstract: Methods for processing of a workpiece are disclosed. The actual rate at which different portions of an ion beam can process a workpiece, referred to as the processing rate profile, is determined by measuring the amount of material removed from, or added to, a workpiece by the ion beam as a function of ion beam position. An initial thickness profile of a workpiece to be processed is determined. Based on the initial thickness profile, a target thickness profile, and the processing rate profile of the ion beam, a first set of processing parameters are determined. The workpiece is then processed using this first set of processing parameters. In some embodiments, an updated thickness profile is determined after the first process and a second set of processing parameters are determined. A second process is performed using the second set of processing parameters. Optimizations to improve throughput are also disclosed.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: November 24, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Morgan D. Evans, Kevin Anglin, Ross Bandy
  • Publication number: 20200194271
    Abstract: A method of patterning a substrate. The method may include providing a cavity in a layer, disposed on the substrate, the cavity having a first length along a first direction and a first width along a second direction, perpendicular to the first direction, and wherein the layer has a first height along a third direction, perpendicular to the first direction and the second direction. The method may include depositing a sacrificial layer over the cavity in a first deposition procedure; and directing angled ions to the cavity in a first exposure, wherein the cavity is etched, and wherein after the first exposure, the cavity has a second length along the first direction, greater than the first length, and wherein the cavity has a second width along the second direction, no greater than the first width.
    Type: Application
    Filed: November 7, 2019
    Publication date: June 18, 2020
    Applicant: APPLIED Materials, Inc.
    Inventors: Kevin Anglin, Simon Ruffell
  • Publication number: 20200126757
    Abstract: Provided herein are approaches for in-situ plasma cleaning of ion beam optics. In one approach, a system includes a component (e.g., a beam-line component) of an ion implanter processing chamber. The system further includes a power supply for supplying a first voltage and first current to the component during a processing mode and a second voltage and second current to the component during a cleaning mode. The second voltage and current are applied to one or more conductive beam optics of the component, individually, to selectively generate plasma around one or more of the one or more conductive beam optics. The system may further include a flow controller for adjusting an injection rate of an etchant gas supplied to the beam-line component, and a vacuum pump for adjusting pressure of an environment of the beam-line component.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 23, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Kevin Anglin, William Davis Lee, Peter Kurunczi, Ryan Downey, Jay T. Scheuer, Alexandre Likhanskii, William M. Holber
  • Patent number: 10553448
    Abstract: A method of processing a layer. The method may include providing the layer on a substrate, the substrate defining a substrate plane; directing an ion beam to an exposed surface of the layer in an ion exposure when the substrate is disposed in a first rotational position, the ion beam having a first ion trajectory, the first ion trajectory extending along a first direction, wherein the first ion trajectory forms a non-zero angle of incidence with respect to a perpendicular to the substrate plane; performing a rotation by rotating the substrate with respect to the ion beam about the perpendicular from the first rotational position to a second rotational position; and directing the ion beam to the exposed surface of the layer in an additional ion exposure along the first ion trajectory when the substrate is disposed in the second rotational position.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: February 4, 2020
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Tristan Y. Ma, Morgan Evans, Kevin Anglin, Robert J. Masci, John Hautala
  • Publication number: 20200027707
    Abstract: A method is provided. The method may include providing a substrate, the substrate comprising a substrate surface, the substrate surface having a three-dimensional shape. The method may further include directing a depositing species from a deposition source to the substrate surface, wherein a layer is deposited on a deposition region of the substrate surface. The method may include performing a substrate scan during the directing or after the directing to transport the substrate from a first position to a second position. The method may also include directing angled ions to the substrate surface, in a presence of the layer, wherein the layer is sputter-etched from a first portion of the deposition region, and wherein the layer remains in a second portion of the deposition region.
    Type: Application
    Filed: July 17, 2018
    Publication date: January 23, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: CHRISTOPHER HATEM, KEVIN ANGLIN
  • Patent number: 10522330
    Abstract: Provided herein are approaches for in-situ plasma cleaning of one or more components of an ion implantation system. In one approach, the component may include a beam-line component having one or more conductive beam optics. The system further includes a power supply for supplying a first voltage and first current to the component during a processing mode and a second voltage and second current to the component during a cleaning mode. The second voltage and current may be applied to the conductive beam optics of the component, in parallel, to selectively (e.g., individually) generate plasma around one or more of the one or more conductive beam optics. The system may further include a flow controller for adjusting an injection rate of an etchant gas supplied to the component, and a vacuum pump for adjusting pressure of an environment of the component.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: December 31, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Kevin Anglin, William Davis Lee, Peter Kurunczi, Ryan Downey, Jay T. Scheuer, Alexandre Likhanskii, William M. Holber
  • Patent number: 10410844
    Abstract: Provided herein are approaches for in-situ plasma cleaning of one or more components of an ion implantation system. In one approach, the component may include a beam-line component, such as an energy purity module, having a plurality of conductive beam optics contained therein. The system further includes a power supply system for supplying a voltage and a current to the beam-line component during a cleaning mode, wherein the power supply system may include a first power plug coupled to a first subset of the plurality of conductive beam optics and a second power plug coupled to a second subset of the plurality of conductive beam optics. During a cleaning mode, the voltage and current may be simultaneously supplied and split between each of the first and second power plugs.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: September 10, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Kevin Anglin, Brant S. Binns, Peter F. Kurunczi, Jay T. Scheuer, Eric Hermanson, Alexandre Likhanskii
  • Publication number: 20190272983
    Abstract: A substrate assembly may include an outer halo, the outer halo comprising a first material and defining a first aperture. The substrate assembly may also include a halo ring, comprising a second material and disposed at least partially within the first aperture. The halo ring may define a second aperture, concentrically positioned within the first aperture, wherein the halo ring is coupled to accommodate a substrate therein.
    Type: Application
    Filed: May 2, 2018
    Publication date: September 5, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Jay Wallace, Simon Ruffell, Kevin Anglin, Tyler Rockwell, Chris Campbell, Kevin M. Daniels, Richard J. Hertel
  • Publication number: 20190256966
    Abstract: A method includes providing a substrate, where the substrate has a patterned substrate surface, wherein the patterned substrate surface comprises a first surface region and a second surface region. The method may also include directing a depositing species to the patterned substrate surface; and directing angled ions to the patterned substrate surface, wherein the depositing species forms a deposit on the first surface region and does not form a deposit on the second surface region.
    Type: Application
    Filed: February 21, 2018
    Publication date: August 22, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Kevin Anglin, Maureen Petterson
  • Patent number: 10269663
    Abstract: An apparatus of a wafer processing apparatus includes at least one memory and logic, at least a portion of which is implemented in circuitry of the wafer processing apparatus including at least one processor coupled to the at least one memory. The logic may provide a 3D model of a surface of a wafer, the wafer defining a wafer plane; and modify a surface feature in a Z-direction along the surface of the wafer based on at least one of: an X-critical dimension (CD) extending along an X-direction of the wafer plane, and a Y-CD extending along a Y direction of the wafer plane.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: April 23, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Morgan D. Evans, Tristan Ma, Kevin Anglin, Motoya Okazaki, Johannes M. van Meer
  • Patent number: 10222202
    Abstract: An apparatus may include a processor and memory unit, including a control routine having a measurement processor to determine, based upon a first set of scatterometry measurements, a first change in a first dimension of a first set of substrate features along a first direction. The first set of substrate features may be elongated along a second direction perpendicular to the first direction. The measurement processor may be to determine, based upon a second set of scatterometry measurements, a second change in dimension of a second set of substrate features along the second direction, wherein the second set of substrate features is elongated along the first direction. The apparatus may include a control processor to generate an error signal when a figure of merit based upon the first change and the second change lies outside a target range.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: March 5, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Morgan D. Evans, Simon Ruffell, Tristan Y. Ma, Kevin Anglin
  • Publication number: 20190027367
    Abstract: Methods for processing of a workpiece are disclosed. The actual rate at which different portions of an ion beam can process a workpiece, referred to as the processing rate profile, is determined by measuring the amount of material removed from, or added to, a workpiece by the ion beam as a function of ion beam position. An initial thickness profile of a workpiece to be processed is determined. Based on the initial thickness profile, a target thickness profile, and the processing rate profile of the ion beam, a first set of processing parameters are determined. The workpiece is then processed using this first set of processing parameters. In some embodiments, an updated thickness profile is determined after the first process and a second set of processing parameters are determined. A second process is performed using the second set of processing parameters. Optimizations to improve throughput are also disclosed.
    Type: Application
    Filed: September 26, 2018
    Publication date: January 24, 2019
    Inventors: Morgan D. Evans, Kevin Anglin, Ross Bandy
  • Publication number: 20180340769
    Abstract: An apparatus may include a processor and memory unit, including a control routine having a measurement processor to determine, based upon a first set of scatterometry measurements, a first change in a first dimension of a first set of substrate features along a first direction. The first set of substrate features may be elongated along a second direction perpendicular to the first direction. The measurement processor may be to determine, based upon a second set of scatterometry measurements, a second change in dimension of a second set of substrate features along the second direction, wherein the second set of substrate features is elongated along the first direction. The apparatus may include a control processor to generate an error signal when a figure of merit based upon the first change and the second change lies outside a target range.
    Type: Application
    Filed: May 25, 2017
    Publication date: November 29, 2018
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Morgan D. Evans, Simon Ruffell, Tristan Y. MA, Kevin Anglin
  • Publication number: 20180197796
    Abstract: An apparatus of a wafer processing apparatus includes at least one memory and logic, at least a portion of which is implemented in circuitry of the wafer processing apparatus including at least one processor coupled to the at least one memory. The logic may provide a 3D model of a surface of a wafer, the wafer defining a wafer plane; and modify a surface feature in a Z-direction along the surface of the wafer based on at least one of: an X-critical dimension (CD) extending along an X-direction of the wafer plane, and a Y-CD extending along a Y direction of the wafer plane.
    Type: Application
    Filed: January 6, 2017
    Publication date: July 12, 2018
    Inventors: Morgan D. Evans, Tristan Ma, Kevin Anglin, Motoya Okazaki, Johannes M. van Meer
  • Publication number: 20180174843
    Abstract: A method of etching a workpiece comprising two or more materials is disclosed. The method involves using physical sputtering as the etching method where the processing parameters of the sputtering process are tuned to achieve a desired etch rate selectivity. The method includes determining the etch rate of each material disposed on the workpiece as a function of various processing parameters, such as ion species, ion energy, incidence angle and temperature. Once the relationship between etch rate and these parameters is determined for each material, a set of values for these processing parameters may be chosen to achieve the desired etch rate selectivity.
    Type: Application
    Filed: December 16, 2016
    Publication date: June 21, 2018
    Inventors: Kevin Anglin, Tristan Ma, Morgan D. Evans, John Hautala, Heyun Yin
  • Patent number: 10002764
    Abstract: A method of etching a workpiece comprising two or more materials is disclosed. The method involves using physical sputtering as the etching method where the processing parameters of the sputtering process are tuned to achieve a desired etch rate selectivity. The method includes determining the etch rate of each material disposed on the workpiece as a function of various processing parameters, such as ion species, ion energy, incidence angle and temperature. Once the relationship between etch rate and these parameters is determined for each material, a set of values for these processing parameters may be chosen to achieve the desired etch rate selectivity.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: June 19, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Kevin Anglin, Tristan Ma, Morgan D. Evans, John Hautala, Heyun Yin