Abstract: A method and apparatus for testing network performance are provided. In data provided by an application on a first host for transport or communication to an application associated with a second host according to a first data transport protocol is intercepted at the first host and wrapped or encapsulated in a test data packet formatted according to a second data transport protocol. The test data packet formatted according to the second data transport protocol includes, in addition to data comprising all or a portion of the original data packet, instrumentation information. The test data packet is then delivered to the second host, which unpacks the original data packet and the instrumentation information. A response packet containing instrumentation information may be sent from the second host to the first host to provide roundtrip performance metrics.

Abstract: An air oxidation hair dye application system and a method for coloring hair using this system are provided. The system includes a container holding the hair dye and a comb-shaped applicator mounted on the container.

Abstract: A system and method are provided for establishing location-based push-to-talk communication groups. A location determining application is incorporated within a communication network for members of a push-to-talk group. This application may include global positioning satellite technology incorporated in mobile communication devices carried by the members, a triangulation application incorporated at a communications server, or an RFID application associated with the members. Location data obtained on the members is maintained in a database that is accessible to a communications server facilitating communication between the members. When a member initiates a push-to-talk communication, other members of the group are contacted based upon their locations. The communication can be selectively transmitted to either those within a pre-designated location, or outside of the pre-designated location.

Abstract: An Interactive Voice Response unit (IVR) is provided that includes a menu structure comprising a plurality of menus, each menu comprising a plurality of options that are selectable by a user, wherein the plurality of menus and each menu's respective plurality of options define a plurality of potential navigation paths for the user through the menu structure and a processor operable to receive, from the user, a request to change the menu structure; effect the requested change to the menu structure; and associate the changed menu structure with the requesting user.

Abstract: A method for designing a system on a target device includes merging a post-fit netlist for a first partition of the system from a set-up compilation with a post-synthesis netlist for a second partition of the system from an incremental compilation to form a combined netlist. Fitting is performed on the combined netlist.

Abstract: A method and apparatus for process optimization is provided. Process optimization improves parametric and functional yield post mask manufacturing.

Abstract: A method and apparatus for modeling and cross correlation of design predicted criticalities include a feedback loop where information from the manufacturing process is provided to cross correlation engine for optimization of semiconductor manufacturing. The information may include parametric information, functional information, and hot spots determination. The sharing of information allows for design intent to be reflected in manufacturing metrology space; thus, allowing for more intelligent metrology and reduces cycle time.

Abstract: A method and apparatus for inspection optimization is provided. Inspection optimization improves the parametric and functional yield using optimized inspection lists for in-line semiconductor manufacturing metrology and inspection equipment.

Abstract: A method and apparatus for mask optimization is provided. Mask design and production is optimized by providing proper weighting parameters for critical features. The parameters may include information such as parametric information, functional information, and hot spots determination.

Abstract: Techniques are provided for converting a circuit design file so that it is compatible with a new programmable IC. Black box declarations and instances of black boxes in the circuit design file are located automatically. Then, information about the function and structure of the black boxes is gathered from various user files. This information is used to convert the black box declarations and instances into equivalent declarations and instances that are compatible with the new programmable IC. The design conversion process is performed quickly and automatically with minimal user input. User input is only needed to identify recognized black boxes.

Abstract: In a transmitter that includes a plurality of partitioned DAC processing cells coupled to a corresponding plurality of partitioned encoder processing cells, a method for processing signals may include aggregating outputs of each of the plurality of partitioned DAC processing cells to generate an analog output signal. The transmitter may be a direct drive transmitter. The generated analog output signal may be a reduced emissions analog signal. The plurality of encoder processing cells may be partitioned into at least a group of odd encoder processing cells and a group of even encoder processing cells. The plurality of DAC processing cells may be partitioned into at least a group of odd DAC processing cells for processing outputs of the group of odd encoder processing cells and a group of even DAC processing cells for processing outputs of the group of even encoder processing cells.

Abstract: A method and apparatus for determining operational preferences for a user access to a plurality of telecommunication response systems designating by the user that user operations of one of the plurality of telecommunication response systems will be the operational preferences of the user for all of the plurality of telecommunication response systems; storing the operational preferences for the user; accessing the stored operational preferences by a second one of the plurality of telecommunication response systems for use in communicating with the user during interactions with the user by the second one of plurality of telecommunication response systems; and interpreting user operations by the second one of plurality of telecommunication response systems using the accessed operational preferences.

Abstract: Adding at least one non-silicon precursor (such as a germanium precursor, a carbon precursor, etc.) during formation of a silicon nitride, silicon oxide, silicon oxynitride or silicon carbide film improves the deposition rate and/or makes possible tuning of properties of the film, such as tuning of the stress of the film. Also, in a doped silicon oxide or doped silicon nitride or other doped structure, the presence of the dopant may be used for measuring a signal associated with the dopant, as an etch-stop or otherwise for achieving control during etching.

Abstract: A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.

Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.

Abstract: A programmable channel-swap crossbar switch for swapping signal flow from one channel to another within an Ethernet physical layer device (PHY) is presented. The crossbar switch includes two or more programmed multiplexers, each multiplexer configured to receive two or more input signals and to select which one of the input signals to pass to a programmed corresponding channel, such that a first input signal associated with a first channel can be swapped to a second channel as operating conditions necessitate. The crossbar switch can be used for Ethernet communications with various communication speeds, such as 10BaseT, 100BaseT, and Gigabit communications. A crossbar switch can be used in both a transmit path and a receive path. Two crossbar switches may be used in a receive path in order to undo channel swapping for control signal processing. A method of channel-swapping in an Ethernet PHY communications system is also presented.

Abstract: A method and apparatus protect data stored in a device by storing data from the device on a backup system upon the device being connected to the backup system; detecting that the device has been lost or stolen; encrypting a set of data stored on the device that has not been stored on the backup system using an encryption key based on another set of data stored on the device and also stored on the backup system; and deleting the other set of data and encryption key from the device.

Abstract: A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4 A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

Abstract: A physical layer device (PLD) includes a first serializer-deserializer (SERDES) device and a second SERDES device. Each SERDES device includes an analog portion with a serial port that is configured to communicate serial data with various network devices, and a digital portion that is configured to communicate parallel data with other various network devices. The PLD includes a first signal path that is configured to route serial data signals between the analog portions of the SERDES devices, bypassing the digital portions of the SERDES devices. Therefore, the SERDES devices can directly communicate serial data without performing parallel data conversion. A second signal path is configured to route recovered clock and data signals between the analog portions of the SERDES devices, but still bypassing the digital portions of the SERDES devices. The recovered clock and data signals are then regenerated before being transmitted over a network device.

Abstract: The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions of the wafers where p-MOSFETs are fabricated. The structures are fabricated by first forming a damaged region with a surface of a Si-containing substrate by ion implanting of a light atom such as He. A strained SiGe alloy is then formed on the Si-containing substrate containing the damaged region. An annealing step is then employed to cause substantial relaxation of the strained SiGe alloy via a defect initiated strain relaxation. Next, a strained semiconductor cap such as strained Si is formed on the relaxed SiGe alloy.