Abstract: A method and apparatus provide means for saving and restoring processor register values and allocating and deallocating stack memory. A first field of a save instruction encodes whether a value in a register of a processor is saved as a static value. A second field of the save instruction encodes whether a value in a register of a processor is saved as an argument value. A third field of the save instruction encodes a size of a stack frame created during execution of the save instruction. An argument value is saved in a calling program's stack frame. A static value is saved in a called program's stack frame. A restore instruction is used to restore static values and deallocate the stack frame. The save and restore instructions may be executed using any programmable device, including a single instruction set architecture processor or a multi-instruction set architecture processor.

Abstract: A multiprocessing system, including a multithreading microprocessor and a multiprocessor operating system (OS), is disclosed. The microprocessor includes a plurality of thread contexts (TCs), each having a program counter and a general purpose register set for executing a thread. The OS includes a data structure having an entry for each of the plurality of TCs, each entry containing information describing capabilities of the corresponding one of the plurality of TCs. Each entry further comprises a TC identifier field for identifying a corresponding one of the plurality of TCs. The OS populates the TC identifier field for each of the entries with a unique identifier value.

Abstract: a multiprocessing system, including a multithreading microprocessor and a multiprocessor operating system (OS), is disclosed. The microprocessor includes a plurality of thread contexts (TCs) configured as an array, each having a program counter, a general purpose register set for executing a thread, and a register for storing an index of the respective TC within the array. The OS maintains a table of entries, each the entry for storing a CPU-unique value for a respective one of the TCs. The OS comprises a respective thread configured to execute on each of the respective TCs and to read the index from the register of the respective one of the TCs and to read the respective CPU-unique value for the respective one of the TCs using the index.

Abstract: A multiprocessing system, including a multithreading microprocessor and a multiprocessor operating system (OS), is disclosed. The microprocessor includes a plurality of thread contexts (TCs), each having a program counter and a general purpose register set for executing a thread. The microprocessor also includes a translation lookaside buffer (TLB), shared by the plurality of TCs rather than being replicated for each of the plurality of TCs, and privileged to be managed only by operating system-privileged threads rather than by user-privileged threads. The OS manages the TLB, and schedules execution of both the operating system-privileged threads and the user-privileged threads on the plurality of TCs.

Abstract: A RISC processor having a data mover engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instruction. The read-tie, single write-tie, and dual write-tie instructions are used to associate software accessible register addresses with memory addresses. These associations effect the operation of the data mover engine such that, for the duration of the associations, the data mover engine routes data to and from associated memory addresses and the execution unit of the processor in response to instructions that specify moving data to and from the associated register addresses. The invention reduces the number of instructions and hardware overhead associated with implementing program loops in a RISC processor.

Abstract: A fork instruction for execution on a multithreaded microprocessor and occupying a single instruction issue slot is disclosed. The fork instruction, executing in a parent thread, includes a first operand specifying the initial instruction address of a new thread and a second operand. The microprocessor executes the fork instruction by allocating context for the new thread, copying the first operand to a program counter of the new thread context, copying the second operand to a register of the new thread context, and scheduling the new thread for execution. If no new thread context is free for allocation, the microprocessor raises an exception to the fork instruction. The fork instruction is efficient because it does not copy the parent thread general purpose registers to the new thread. The second operand is typically used as a pointer to a data structure in memory containing initial general purpose register set values for the new thread.

Abstract: Polynomial arithmetic instructions are provided in an instruction set architecture (ISA). A multiply-add-polynomial (MADDP) instruction and a multiply-polynomial (MULTP) instruction are provided.

Abstract: A shared resource access control system having a gating storage responsive to a plurality of controls with each of the controls derived from an instruction context identifying the shared resource, the gating storage including a plurality of sets of access method functions with each set of access method functions including a first access method function and a second access method function with the gating storage producing a particular one access method function from a particular one set responsive to the controls; and a controller, coupled to the gating storage, for controlling access to the shared resource using the particular one access method function.

Abstract: Mechanisms for dynamically configuring the resources of a virtual multiprocessor are provided. An apparatus to configure resources for virtual processing elements in a virtual multiprocessor is provided. The apparatus includes a virtual multiprocessor context, virtual processing element contexts, and configuration logic. The virtual multiprocessor context, prescribes the resources, and controls a configuration state of the virtual multiprocessor. The virtual processing element contexts each exclusively correspond to a virtual processing element. The virtual processing element contexts each have first logic, for prescribing whether the virtual processing element is permitted to configure the resources; and second logic, for prescribing a subset of the resources that is allocated to the virtual processing element.

Abstract: A microprocessor core includes a plurality of inputs that indicate whether a corresponding plurality of independently occurring events has occurred. The inputs are non-memory address inputs. The core also includes a yield instruction in its instruction set architecture, comprising a user-visible output operand and an explicit input operand. The input operand specifies one or more of the independently occurring events. The yield instruction instructs the microprocessor core to suspend issuing for execution instructions of a program thread until at least one of the independently occurring events specified by the input operand has occurred. The program thread contains the yield instruction. The yield instruction further instructs the microprocessor core to return a value in the output operand indicating which of the independently occurring events occurred to cause the microprocessor core to resume issuing the instructions of the program thread.

Abstract: A multiprocessing system including a multithreading microprocessor and multiprocessor operating system (OS) is disclosed. The microprocessor includes a first and a second plurality of thread contexts (TCs), each TC having a program counter and a general purpose register set for executing a thread. The microprocessor also includes a first and a second shared privileged resource, shared by the first and second respective plurality of TCs rather than being replicated for each of the respective first and second plurality of TCs, and privileged to be managed only by operating system-privileged threads rather than by user-privileged threads. The OS manages the first and second shared privileged resource and schedules execution of both the operating system-privileged threads and the user-privileged threads on the plurality of TCs.

Abstract: An apparatus and method are provided that disassociates the power consumed by a processing system from the instructions that it executes. The apparatus includes a power predictor that predicts the power that will be consumed by the processing system during execution of particular instructions, and a subsystem inhibition control, that selectively turns on/off available subsystems within the processing system based on the power that is predicted to be consumed. By predicting the power that will be consumed during execution, and by selectively turning on/off particular subsystems, the total power consumed by the processing system can be made invariant, or random. In either case, a counterweight current can be added to the processing system, depending on which of the subsystems are available to be turned on/off, and which are turned on/off, to further disassociate the total power consumed by the processing system from the instructions it is executing.

Abstract: An extendable instruction set architecture is provided. In an embodiment, a microprocessor includes a memory, a virtual instruction expansion store, and substitution logic. The memory stores at least one virtual instruction that includes an index and at least one parameter. The virtual instruction expansion store includes at least one instruction template and at least one parameter selector. The substitution logic forms a sequence of at least one expanded instruction. In an example, each expanded instruction is based on an instruction template and includes a new parameter for use with the instruction template. The new parameter is generated by performing a logical operation from the parameter selector on one or more parameter of the virtual instruction.

Abstract: A bifurcated instruction scheduler for dispatching instructions of multiple threads concurrently executing in a multithreading processor is provided. The scheduler includes a first portion within a reusable core that is not customizable by a customer, a second portion outside the core that is customizable, and an interface coupling the second portion to the core. The second portion implements a thread scheduling policy that may be customized to the customer's particular application. The first portion may be scheduling policy-agnostic and issues instructions of the threads each clock cycle to execution units based on the scheduling policy communicated by the second portion. The second portion communicates the scheduling policy via a priority for each of the threads. When the core commits an instruction for execution, the core communicates to the second portion which thread the committed instruction is in to enable the second portion to update the priorities in response thereto.

Abstract: A fork instruction for execution on a multithreaded microprocessor and occupying a single instruction issue slot is disclosed. The fork instruction, executing in a parent thread, includes a first operand specifying the initial instruction address of a new thread and a second operand. The microprocessor executes the fork instruction by allocating context for the new thread, copying the first operand to a program counter of the new thread context, copying the second operand to a register of the new thread context, and scheduling the new thread for execution. If no new thread context is free for allocation, the microprocessor raises an exception to the fork instruction. The fork instruction is efficient because it does not copy the parent thread general purpose registers to the new thread. The second operand is typically used as a pointer to a data structure in memory containing initial general purpose register set values for the new thread.

Abstract: A memory interface for use with a multiprocess memory system having a gating memory, the gating memory associating one or more memory access methods with each of a plurality of memory locations of the memory system wherein the gating memory returns a particular one access method for a particular one memory location responsive to a memory access instruction relating to the particular one memory location, the interface including: a request storage for storing a plurality of concurrent memory access instructions for one or more of the particular memory locations, each the memory access instruction issued from an associated independent thread context; an arbiter, coupled to the request storage, for selecting a particular one of the memory access instructions to apply to the gating memory; and a controller, coupled to the request storage and to the arbiter, for: storing the plurality of memory access instructions in the request storage; initiating application of the particular one memory access instruction selecte

Abstract: A configurable instruction set architecture is provided whereby a single virtual instruction may be used to generate a sequence of instructions. Dynamic parameter substitution may be used to substitute parameters specified by a virtual instruction into instructions within a virtual instruction sequence.

Abstract: A multithreading microprocessor is disclosed. The microprocessor includes a plurality of thread contexts. The microprocessor provides instructions that enable a thread context issuing the instructions to move a value between itself and a target thread context distinct from the issuing thread context independent of cooperation from the target thread context. The instructions employ an operand to specify the target thread context. In one embodiment, the microprocessor is also a virtual multiprocessor including a plurality of virtual processing elements. Each virtual processing element includes a plurality of thread contexts. The instructions also employ a second operand to specify the target virtual processing element.

Abstract: A multiprocessing system is disclosed. The system includes a multithreading microprocessor including a plurality of thread contexts (TCs), each having a program counter and a general purpose register set for executing a thread. The microprocessor also includes a shared privileged resource, shared by the plurality of TCs rather than being replicated for each of the plurality of TCs, and privileged to be managed only by operating system-privileged threads rather than by user-privileged threads. The system also includes a multiprocessor operating system (OS), configured to manage the shared privileged resource, and to schedule execution of both the operating system-privileged threads and the user-privileged threads on the plurality of TCs.

Abstract: A microprocessor core includes a plurality of inputs that indicate whether a corresponding plurality of independently occurring events has occurred. The inputs are non-memory address inputs. The core also includes a yield instruction in its instruction set architecture, comprising a user-visible output operand and an explicit input operand. The input operand specifies one or more of the independently occurring events. The yield instruction instructs the microprocessor core to suspend issuing for execution instructions of a program thread until at least one of the independently occurring events specified by the input operand has occurred. The program thread contains the yield instruction. The yield instruction further instructs the microprocessor core to return a value in the output operand indicating which of the independently occurring events occurred to cause the microprocessor core to resume issuing the instructions of the program thread.