Abstract: A mechanism for assuring quality of service for a context in a digital processor has a first scheduling register dedicated to the context, the register having N out of M bits set, and a first scheduler that consults the register to assign issue slots to the context. The first scheduler grants issue slots for the context by referencing the N bits in the first register, and repeats a pattern of assignments of issue slots after referencing the M bits of the first register.

Abstract: A microprocessor includes a core configured to concurrently execute instructions of a plurality of program threads and a yield instruction, included in the instruction set of the microprocessor. The yield instruction includes an opcode for instructing the microprocessor core to suspend issuing instructions of a thread. The thread is one of the plurality of concurrently executed program threads. The yield instruction is an instruction in the thread. The yield instruction also includes a first operand. If the first operand is a first predetermined value the microprocessor core terminates issuing instructions of the thread. If the first operand is a second predetermined value the microprocessor core unconditionally reschedules issuing instructions of the thread. The yield instruction also includes a second operand for receiving a result value of the instruction usable by other instructions of the program thread.

Abstract: Provided is a method and system for encoding an instruction to restore processor core register values. The method includes encoding in a first field of the instruction whether a first value, in a stack memory location having an address value equal to A plus a second value in a second register, is to be restored to a first register. A third value is encoded in a second field of the instruction for adjusting the second value in the second register.

Abstract: Partial bitwise permutation instructions are provided in a microprocessor or microcontroller. Partial bitwise permutations may be specified by one or more of the following: a destination specifier, a previous partial value source, a destination subset specifier, and a control specifier.

Abstract: An extendable instruction set architecture is provided. In an embodiment, a microprocessor includes a memory, a virtual instruction expansion store, and substitution logic. The memory stores at least one virtual instruction that includes an index and at least one parameter. The virtual instruction expansion store includes at least one instruction template and at least one parameter selector. The substitution logic forms a sequence of at least one expanded instruction. In a example, the substitution logic sign-extends the at least one parameter to form an immediate value of the at least one expanded instruction in a manner specified by the at least one parameter selector. In another example, the substitution logic concatenates a first parameter and a second parameter of the virtual instruction to form an immediate value of the at least one expanded instruction in a manner specified by the at lest one parameter selector.

Abstract: A method and apparatus within a computer processing environment is provided for proxy management of a plurality of memory management units connected to a plurality of processing elements or cores within a unified memory environment. The proxy management system includes a proxy processor, such as a RISC core, and proxy memory management units that translate virtual memory requests generated by each of the processing elements into physical address. If the virtual memory requests can be translated directly into a physical address, then the translation is performed and the memory request proceeds. However, if the virtual address cannot be translated into a physical address by the proxy memory management unit, then the unit alerts the proxy processor to perform a page table lookup to locate the physical address. The lookup updates the table in the proxy memory management unit and the memory access proceeds. Such lookup is transparent to the processing element that generated the memory access.

Abstract: A method and apparatus within a processing environment is provided for proxy management of a plurality of proxy caches connected to a plurality of processing elements or cores within a unified memory environment. The proxy management system includes a proxy processor, such as a RISC core, that monitors data transfers or ownership transfers between the processing elements. If the proxy processor determines that a data transfer in one of the proxy caches will affect the coherency within another proxy cache, the proxy processor executes proxy management instructions such as invalidate, flush, prefetch to the appropriate proxy caches to insure coherency between the proxy caches and the unified memory.

Abstract: An apparatus and method are provided that disassociates the power consumed by a processing system from the instructions that it executes. The apparatus includes a power predictor that predicts the power that will be consumed by the processing system during execution of particular instructions, and a subsystem inhibition control, that selectively turns on/off available subsystems within the processing system based on the power that is predicted to be consumed. By predicting the power that will be consumed during execution, and by selectively turning on/off particular subsystems, the total power consumed by the processing system can be made invariant, or random. In either case, a counterweight current can be added to the processing system, depending on which of the subsystems are available to be turned on/off, and which are turned on/off, to further disassociate the total power consumed by the processing system from the instructions it is executing.

Abstract: A method and apparatus provide means for saving and restoring processor register values and allocating and deallocating stack memory. A first field of a save instruction encodes whether a value in a register of a processor is saved as an argument value or a static value. A second field of the save instruction encodes a size of a stack frame created during execution of the save instruction. An argument value is saved in a calling program's stack frame. A static value is saved in a called program's stack frame. A restore instruction is used to restore static values and deallocate the stack frame. The save and restore instructions may be executed using any programmable device, including a single instruction set architecture processor or a multi-instruction set architecture processor.

Abstract: An apparatus and method are provided to enable programmable page table accesses in a virtual memory system. The apparatus includes context logic and context configuration logic. The context logic designates an entry within a data structure. The context logic has a plurality of fields, where each of the plurality of fields provides part of a pointer to the entry. The context configuration logic is coupled to the context logic. The context configuration logic prescribes the structure of the each of the plurality of fields. Programming the context configuration logic determines the function by which the context logic derives a useful value from a virtual address associated with an event.

Abstract: An apparatus and method are provided that enable a central processing unit (CPU) to extend the attributes of virtual memory beyond that which an existing translation lookaside buffer within the CPU is capable of storing while at the same time preserving compatibility with legacy operating system software. The apparatus includes a translation lookaside buffer and extended attributes logic. The translation lookaside buffer (TLB) stores a plurality of TLB entries. Each of the TLB entries has an extended memory attributes index field. The extended attributes logic is coupled to the TLB. The extended attributes logic employs the extended memory attributes index field to access one of a plurality of extended memory attributes registers that is external to the TLB. Contents of the extended memory attributes register prescribe specific extended properties for a corresponding virtual memory page.

Abstract: An apparatus and method are provided that enable a central processing unit (CPU) to extend the protection schemes afforded to virtual memory beyond that which an existing translation lookaside buffer within the CPU is capable providing while at the same time preserving compatibility with legacy operating system software. The apparatus includes a translation lookaside buffer (TLB) and extended protection logic. The translation lookaside buffer (TLB) stores a plurality of TLB entries, where each TLB entry of the plurality of TLB entries has a flags field and an extended flags field. The extended protection logic is coupled to the TLB. The extended protection logic specifies legacy access restrictions according to the flags field, and specifies the extended access restrictions according to the flags field in combination with the extended flags field. Specification of the legacy access restrictions preserves compatibility with a legacy virtual page access protocol.

Abstract: An apparatus and method are provided that disassociates the power consumed by a processing device from the instructions that are executing, on a clock-by-clock basis. The apparatus includes a power predictor that predicts the power that will be consumed by the processing device during execution of particular instructions, and a power counterweight, that adds a counterweight current to the total power consumption of the processing device. By predicting the power that will be consumed during execution, and by adding a counterweight current during instruction execution, the total power consumed is made invariant. In another aspect, a random counterweight generator produces a random counterweight current which is added to the power consumed during instruction execution to disassociate the power consumed from the instructions being executed.

Abstract: An apparatus and method are provided that enable system designers to have programmable minimum memory page sizes. The apparatus has a memory management unit (MMU) for storing a plurality of page table entries (PTEs) and a pagegrain register for prescribing a minimum page size. Each of the PTEs in the MMU specifies a page granularity for a corresponding physical memory page, where the page granularity is bounded by the minimum page size. The MMU has and page granularity logic. The page granularity logic determines a page size for the corresponding physical memory page. The page size is determined based on the minimum page size and the page granularity. The pagegrain register prescribes the minimum page size, in default, according to a legacy memory management protocol, and in alternative, as one of the programmable minimum memory page sizes according to an extended memory management protocol.

Abstract: An apparatus and method are provided that enable system designers to have programmable minimum memory page sizes. The apparatus has a memory management unit (MMU) for storing a plurality of page table entries (PTEs) and a pagegrain register for prescribing a minimum page size. Each of the PTEs in the MMU specifies a page granularity for a corresponding physical memory page, where the page granularity is bounded by the minimum page size. The MMU has and page granularity logic. The page granularity logic determines a page size for the corresponding physical memory page. The page size is determined based on the minimum page size and the page granularity. The pagegrain register prescribes the minimum page size, in default, according to a legacy memory management protocol, and in alternative, as one of the programmable minimum memory page sizes according to an extended memory management protocol.

Abstract: A method and apparatus provide means for saving and restoring processor register values and allocating and deallocating stack memory. A first field of a save instruction encodes whether a value in a register of a processor is saved as an argument value or a static value. A second field of the save instruction encodes a size of a stack frame created during execution of the save instruction. An argument value is saved in a calling program's stack frame. A static value is saved in a called program's stack frame. A restore instruction is used to restore static values and deallocate the stack frame. The save and restore instructions may be executed using any programmable device, including a single instruction set architecture processor or a multi-instruction set architecture processor.

Abstract: An apparatus and method are provided that enable a central processing unit (CPU) to extend the protection schemes afforded to virtual memory beyond that which an existing translation lookaside buffer within the CPU is capable providing while at the same time preserving compatibility with legacy operating system software. The apparatus includes a translation lookaside buffer (TLB) and extended protection logic. The translation lookaside buffer (TLB) stores a plurality of TLB entries, where each TLB entry of the plurality of TLB entries has a flags field and an extended flags field. The extended protection logic is coupled to the TLB. The extended protection logic specifies legacy access restrictions according to the flags field, and specifies the extended access restrictions according to the flags field in combination with the extended flags field. Specification of the legacy access restrictions preserves compatibility with a legacy virtual page access protocol.

Abstract: Partial bitwise permutation instructions are provided in a microprocessor or microcontroller. Partial bitwise permutations may be specified by one or more of the following: a destination specifier, a previous partial value source, a destination subset specifier, and a control specifier.

Abstract: A configurable instruction set architecture is provided whereby a single virtual instruction may be used to generate a sequence of instructions. Dynamic parameter substitution may be used to substitute parameters specified by a virtual instruction into instructions within a virtual instruction sequence.

Abstract: Polynomial arithmetic instructions are provided in an instruction set architecture (ISA). A multiply-add-polynomial (MADDP) instruction and a multiply-polynomial (MULTP) instruction are provided.