Abstract: The disclosed embodiments relate to a computer-based system and/or method which automatically, e.g. with minimal, or entirely without, human intervention, identifies, distinguishes, disambiguates or otherwise differentiates among multiple configurable bicycles based on the data reported to the system from the bicycle's data-reporting components, such that the data reported by those components may be associated with a particular bicycle for real-time and/or later review, analysis, etc. More particularly, where one or more data reporting components of a bicycle may change, the disclosed embodiments enable a data gathering system/service to identify, distinguish, disambiguate or otherwise differentiate among multiple bicycles which may use, or have used, one or more of the same components so as to associate the reported data, such as from a particular ride, with the correct bicycle configuration for real-time and/or later review and/or analysis.

Abstract: Immunoconjugates of the Formula (I) include a linking group for linking an antibody targeting ligand (Ab) to a drug (D). Embodiments of such immunoconjugates are useful for delivering the drug to selected cells or tissues, e.g., for the treatment of cancer.

Abstract: Devices for reducing the open circuit voltages of solar systems are described. In one embodiment, a solar system includes a string of a plurality of solar modules having an open circuit voltage. The solar system also includes a device for reducing the open circuit voltage of the string of the plurality of solar modules during an open circuit configuration.

Abstract: Various methods, apparatuses/systems, and media for automating sponsored-search data pipelines are disclosed.

Abstract: Described herein are IC devices that include TFT based memory arrays on both sides of a layer of logic devices. An example IC device includes a support structure (e.g., a substrate) on which one or more logic devices may be implemented. The IC device further includes a first memory cell on one side of the support structure, and a second memory cell on the other side of the support structure, where each of the first memory cell and the second memory cell includes a TFT as an access transistor. Providing TFT based memory cells on both sides of a layer of logic devices allows significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, significantly reducing the footprint area of the memory array with a given memory cell density.

Abstract: Integrated circuit structures having backside power delivery are described. In an example, an integrated circuit structure includes a device layer within a cell boundary, the device layer having a front side and a backside, and the device layer including a source or drain structure. A source or drain trench contact structure is on the front side of the device layer. The source or drain trench contact structure is coupled to the source or drain structure. A metal layer is on the backside of the device layer. A via structure couples the metal layer to the source or drain trench contact structure. The via structure is overlapping and parallel with a cell row boundary of the cell boundary.

Abstract: Dummy gate patterning lines, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a first gate line along a first direction. A second gate line is parallel with the first gate line along the first direction. A third gate line extends between and is continuous with the first gate line and the second gate line along a second direction, the second direction orthogonal to the first direction.

Abstract: Substrate-less electrostatic discharge (ESD) integrated circuit structures, and methods of fabricating substrate-less electrostatic discharge (ESD) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin and a second fin protruding from a semiconductor pedestal. An N-type region is in the first and second fins. A P-type region is in the semiconductor pedestal. A P/N junction is between the N-type region and the P-type region, the P/N junction on or in the semiconductor pedestal.

Abstract: Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages, related to direct chip attach of dies and circuit boards. An example microelectronic assembly includes a die with IC components provided over the die's frontside, and a metallization stack provided over the die's backside. The die further includes die interconnects extending between the frontside and the backside of the die, to electrically couple the IC components and the metallization stack. The assembly further includes backside conductive contacts, provided over the side of the metallization stack facing away from the die, the backside conductive contacts configured to route signals to/from the IC components via the metallization stack and the die interconnects, and configured to be coupled to respective conductive contacts of a circuit board in absence of a package substrate between the die and the circuit board.

Abstract: Substrate-free integrated circuit structures, and methods of fabricating substrate-free integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin, a plurality of gate structures over the fin, and a plurality of alternating P-type epitaxial structures and N-type epitaxial structures between adjacent ones of the plurality of gate structures.

Abstract: Described herein are IC devices that include TFT based memory arrays on both sides of a layer of logic devices. An example IC device includes a support structure (e.g., a substrate) on which one or more logic devices may be implemented. The IC device further includes a first memory cell on one side of the support structure, and a second memory cell on the other side of the support structure, where each of the first memory cell and the second memory cell includes a TFT as an access transistor. Providing TFT based memory cells on both sides of a layer of logic devices allows significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, significantly reducing the footprint area of the memory array with a given memory cell density.

Abstract: Described herein are IC devices that include TFT based memory arrays on both sides of a layer of logic devices. An example IC device includes a support structure (e.g., a substrate) on which one or more logic devices may be implemented. The IC device further includes a first memory cell on one side of the support structure, and a second memory cell on the other side of the support structure, where each of the first memory cell and the second memory cell includes a TFT as an access transistor. Providing TFT based memory cells on both sides of a layer of logic devices allows significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, significantly reducing the footprint area of the memory array with a given memory cell density.

Abstract: A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include monocrystalline silicon. An epitaxial source material is coupled to a first end of the first and second channel layers. An epitaxial drain material is coupled to a second end of the first and second channel layers, a gate electrode is between the epitaxial source material and the epitaxial drain material, and around the first channel layer and around the second channel layer. The transistor structure further includes a first gate dielectric layer between the gate electrode and each of the first channel layer and the second channel layer, where the first gate dielectric layer has a first dielectric constant. A second gate dielectric layer is between the first gate dielectric layer and the gate electrode, where the second gate dielectric layer has a second dielectric constant.

Abstract: Systems, methods, and computer-readable media, are disclosed in which a variety of data describing the condition of an object can be obtained and probabilistic likelihoods of causes and/or value of damages to the object can be calculated. In a variety of embodiments, data obtained from third-party systems can be utilized in these calculations. Any of a number of machine classifiers can be utilized to generate the probabilistic likelihoods and confidence metrics in the calculated liabilities. A variety of user interfaces for efficiently obtaining and visualizing the object, the surrounding geographic conditions, and/or the probabilistic likelihoods can further be utilized as appropriate. User interfaces can include a scene sketch tool application program interface and/or a liability tool user interface and various data sources can be used to dynamically generate diagrams of object damage and/or the environment in which the object was damaged.

Abstract: Described herein are IC devices that include TFT based memory arrays on both sides of a layer of logic devices. An example IC device includes a support structure (e.g., a substrate) on which one or more logic devices may be implemented. The IC device further includes a first memory cell on one side of the support structure, and a second memory cell on the other side of the support structure, where each of the first memory cell and the second memory cell includes a TFT as an access transistor. Providing TFT based memory cells on both sides of a layer of logic devices allows significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, significantly reducing the footprint area of the memory array with a given memory cell density.

Abstract: A wire management device is disclosed. The device comprises a clip comprising an upper planar member and a lower planar member, each planar member having an inner and outer surface, wherein the inner surface of the upper planar member includes a post extending toward the inner surface of the lower planar member, a stem extending from the outer surface of the lower planar member, the stem including two outwardly-extending flanges, each of the first and second outwardly-extending flanges including an edge portion extending toward the outer surface of the lower planar member, and a transverse passage extending along the outer surface of the lower planar member, the transverse passage extending across the stem, wherein the stem has a recessed portion along the transverse passage.

Abstract: Methods, systems, and computer readable media are disclosed for monitoring photovoltaic solar systems. In some examples, the system includes a solar power measurement input for coupling to a solar panel system, a measurement circuit configured to measure power produced by the solar panel system using the solar power measurement input, and a data transmission system. The measurement circuit is configured, by virtue of the measurement circuit including electrical components rated to at least a certain tolerance level, to take revenue-grade power measurements from the solar power measurement input with a level of accuracy that meets a national or international metering standard. The data transmission system is configured to transmit the revenue-grade power measurements from the measurement circuit to a remote system.

Abstract: Methods, systems, and computer readable media are disclosed for thermal management of a system of one or more electric components. In some examples, the system includes a housing, one or more electric components, one or more temperature sensors on or in the housing, and a thermal management circuit coupled to the electric components and the temperature sensors. The thermal management circuit is configured to monitor the temperature sensors and, based on monitoring the temperature sensors, cause at least a first electric component to curtail power consumption, thereby reducing heat generating by the first electric component.

Abstract: Methods, systems, and computer readable media are disclosed for thermal management of a system of one or more electric components. In some examples, the system includes a housing, one or more electric components, one or more temperature sensors on or in the housing, and a thermal management circuit coupled to the electric components and the temperature sensors. The thermal management circuit is configured to monitor the temperature sensors and, based on monitoring the temperature sensors, cause at least a first electric component to curtail power consumption, thereby reducing heat generating by the first electric component.

Abstract: Methods, systems, and computer readable media are disclosed for monitoring photovoltaic solar systems. In some examples, the system includes a solar power measurement input for coupling to a solar panel system, a measurement circuit configured to measure power produced by the solar panel system using the solar power measurement input, and a data transmission system. The measurement circuit is configured, by virtue of the measurement circuit including electrical components rated to at least a certain tolerance level, to take revenue-grade power measurements from the solar power measurement input with a level of accuracy that meets a national or international metering standard. The data transmission system is configured to transmit the revenue-grade power measurements from the measurement circuit to a remote system.