Abstract: A fluidic device, instrument, and method for processing a biological sample is disclosed herein. An example of the fluidic device includes structures (e.g., sample holder(s), reaction chamber(s), reagent storage zone(s), metering compartment(s), reaction well(s), detection well(s), channel(s), etc.) for efficiently processing sample components and providing expression levels of various biomarker components for characterization of a sample.

Abstract: A series of piperidine-substituted benzoic acid compounds and the use thereof, and specifically disclosed is a compound represented by formula (I) and a pharmaceutically acceptable salt thereof.

Abstract: An electronic device may be provided with an antenna having a resonating element and a light source module mounted to a flexible printed circuit and a metal cowling. The module may emit light through a rear housing wall. The printed circuit may be interposed between the metal cowling and a conductive support plate in the rear housing wall. The printed circuit may include a ground trace coupled to the resonating element. A dimpled pad may couple the ground trace to the support plate. Compressive foam may be used to exert a force against the flexible printed circuit that presses the dimpled pad against the conductive support plate. The ground trace and the dimpled pad may form a return path to ground for the resonating element. The dimpled pad may occupy less height within the device than other structures such as metal springs.

Abstract: An apparatus for detecting the presence of assembly related defects on a semiconductor device including an edge ring having a resistance value and including one or more layers configured to at least partially cover the semiconductor device in a first direction. The one or more layers are divided into a first section and a second section. Each layer of the one or more layers are in electrical communication with one another. The resistance value of the edge ring is at a first resistance value associated with the first and second sections being intact. At least one of the first section and second section is configured to break in response to an assembly related defect, and the resistance value of the edge ring is configured to change from the first resistance value to a second resistance value in response to at least one of the first and second sections being broken.

Abstract: An apparatus for detecting the presence of assembly related defects on a semiconductor device including an edge ring having a resistance value and including one or more layers configured to at least partially cover the semiconductor device in a first direction. The one or more layers are divided into a first section and a second section. Each layer of the one or more layers are in electrical communication with one another. The resistance value of the edge ring is at a first resistance value associated with the first and second sections being intact. At least one of the first section and second section is configured to break in response to an assembly related defect, and the resistance value of the edge ring is configured to change from the first resistance value to a second resistance value in response to at least one of the first and second sections being broken.

Abstract: A system and method for assessing digital interactions with a digital third party accounts can include receiving user account credentials for authentication with an external computing system, storing the user account credentials in association with a authentication token and communicating the authentication token to a computing device of an external application service; receiving, through a programmatic communication interface, a request that references the authentication token and digital interaction details; programmatically authenticating, using the stored user account credentials, as a user account with the external computing system and retrieving account data; processing the account data in combination with the digital interaction details and thereby generating a digital interact assessment; and initiating execution of a digital interaction based in part on the digital interaction assessment.

Abstract: A neural network may be trained on a training corpus that comprises a large number of dataset-visualization pairs. Each pair in the training corpus may consist of a dataset and a visualization of the dataset. The visualization may be a chart, plot or diagram. In each dataset-visualization pair in the training corpus, the visualization may be created by a human making design choices. The neural network may be trained to predict, for a given dataset, a visualization that a human would create to represent the given dataset. During training, features and design choices may be extracted from the dataset and visualization, respectively, in each dataset-visualization pair in the training corpus. After the neural network is trained, features may be extracted from a new dataset, and the trained neural network may predict design choices that a human would make to create a visualization that represents the new dataset.

Abstract: A handle for easily and quickly deploying a shelter wherein a conventional “instant” type shelter is provided having a deployment handle made of webbing material attached to the upper corner of diagonally opposed shelter frame comers, allowing the users to grasp the deployment handles and move outward from each other to expand the shelter frame to its full footprint prior to raising the frame to its desired height and locking it in place.

Abstract: Reconstitution techniques for semiconductor packages are provided. One reconstitution technique is used to encapsulate a plurality of semiconductor packages into a single multi-chip module. Solder balls coupled to each package may be partially exposed after reconstitution, which enables the packages to be coupled to another device. Another reconstitution technique is used to couple a plurality of semiconductor packages into a package-on-package module using self-alignment feature(s). The self-alignment feature(s) are exposed solder ball(s) that are included in the bottom package of the package-on-package module. The exposed solder ball(s) serve as a frame of reference to other solder balls that are encapsulated by an encapsulation material. After the location of these other solders balls are determined, through-mold vias may be formed in the encapsulation material at locations corresponding to the other solder balls.

Abstract: Methods, systems, and apparatuses for printing under bump metallization (UBM) features on chips/wafers are provided. A wafer is received that has a surface defined by a plurality of integrated circuit regions. Each integrated circuit region has a passivation layer and a plurality of terminals on the surface of the wafer accessible through openings in the passivation layer. A plurality of UBM features are formed on the surface of the wafer in the form of an ink such that each UBM feature is formed electrically coupled with a corresponding terminal of the plurality of terminals. An ink jet printer may be used to print the ink in the form of the UBM feature. A UBM feature may be formed directly on a corresponding terminal, or on routing that is coupled to the corresponding terminal. A bump interconnect may be formed on the UBM feature.

Abstract: Methods, systems, and apparatuses for an integrated circuit package assembly process are provided. A wafer is received having a surface defined by a plurality of integrated circuit regions. Electrical conductors are accessible through corresponding first openings in a first passivation layer on the surface of the wafer. Solderable metal layer features are formed on the electrical conductors through the first openings. The wafer is singulated to form a plurality of flip chip dies. A plurality of package substrates is received. Each package substrate has a plurality of solder on pad (SOP) features on a respective surface. Each flip chip die is mounted to a corresponding package substrate such that each SOP feature is coupled to a corresponding solderable metal layer feature, to form a plurality of integrated circuit packages.

Abstract: Methods, systems, and apparatuses for printing under bump metallization (UBM) features on chips/wafers are provided. A wafer is received that has a surface defined by a plurality of integrated circuit regions. Each integrated circuit region has a passivation layer and a plurality of terminals on the surface of the wafer accessible through openings in the passivation layer. A plurality of UBM features are formed on the surface of the wafer in the form of an ink such that each UBM feature is formed electrically coupled with a corresponding terminal of the plurality of terminals. An ink jet printer may be used to print the ink in the form of the UBM feature. A UBM feature may be formed directly on a corresponding terminal, or on routing that is coupled to the corresponding terminal. A bump interconnect may be formed on the UBM feature.

Abstract: Methods, systems, and apparatuses for an integrated circuit package assembly process are provided. A wafer is received having a surface defined by a plurality of integrated circuit regions. Electrical conductors are accessible through corresponding first openings in a first passivation layer on the surface of the wafer. Solderable metal layer features are formed on the electrical conductors through the first openings. The wafer is singulated to form a plurality of flip chip dies. A plurality of package substrates is received. Each package substrate has a plurality of solder on pad (SOP) features on a respective surface. Each flip chip die is mounted to a corresponding package substrate such that each SOP feature is coupled to a corresponding solderable metal layer feature, to form a plurality of integrated circuit packages.

Abstract: Methods, systems, and apparatuses for wafer-level integrated circuit (IC) packages are described. A wafer has a surface defined by a plurality of integrated circuit regions Each integrated circuit region has a passivation layer and a plurality of terminals on the surface of the wafer accessible through openings in the passivation layer. An ink jet printer is configured to print a plurality of routing interconnects on the surface of a wafer in the form of an ink. The ink jet printer is configured to print the plurality of routing interconnects such that each routing interconnect has a first portion in contact with a respective terminal of the plurality of terminals and has a second portion that extends over the passivation layer. Bump interconnects are attached to the routing interconnects. The wafer may be singulated to create a plurality of wafer-level integrated circuits.

Abstract: The semiconductor portion of a circuit includes a plurality of flip chip devices which are arranged in a planar fashion in a common housing. The plurality of flip chip devices are connected to each other without wire bonding. The common housing includes a packaging structure, the packaging structure including a connective portion and at least one web portion, which aids in the thermal management of the heat emitted by the plurality of flip chip devices and which connects the flip chip devices to each other. Passive devices in the circuit may also be arranged in a planar fashion in the common housing.

Abstract: A gas burner with thermoelectric unit installed inside the burner head to generate electricity with waste heat energy. Gas flame at the edge of the burner head creates high temperature source (hot side) for the thermoelectric unit. A heat sink is installed inside the burner head and cooled by the fuel mixture. Electricity is generated by the thermoelectric unit when the gas burner is in operation. The electricity generated by the thermoelectric unit can be used to power electric devices.

Abstract: A gas burner generates electricity with waste heat energy. At least one thermoelectric unit is installed underneath the burner cap of the gas burner. Gas flame at the edge of the burner cap creates heat sources (hot side) for the thermoelectric unit. A gas-mixing chamber underneath the thermoelectric unit functions as heat sinks (cold side) for the thermoelectric unit. An insulation plate is inserted in between the thermoelectric unit and the burner cap to control the hot side temperature. The thermoelectric unit generates electricity while the gas burner is in use and the flame heats up the burner cap. The thermoelectric unit connects to an electric circuit and provides electricity to power devices such as electric fans, lights, TVs, battery chargers etc.

Abstract: The semiconductor portion of a circuit includes a plurality of flip chip devices which are arranged in a planar fashion in a common housing. The plurality of flip chip devices are connected to each other without wire bonding. The common housing includes a packaging structure, the packaging structure including a connective portion and at least one web portion, which aids in the thermal management of the heat emitted by the plurality of flip chip devices and which connects the flip chip devices to each other. Passive devices in the circuit may also be arranged in a planar fashion in the common housing.

Abstract: Disclosed is a method of modifying one or more colors contained in an Encapsulated PostScript (EPS) file in a computer program such as a desktop publishing program (50). After an EPS file has been imported into a publication, all identifiable colors in the EPS file, i.e., spot colors and, in some instances, process colors, are displayed to a color palette (84). The color palette allows a user to see those colors (or inks) that are needed to print the publication, and subsequently modify the colors without having to return to the originating program that exported the EPS file. The method includes creating a publication color list that contains those colors that have been modified, generating a PostScript (PS) color table from the publication color list after the modifications are complete, and changing the attributes of those colors in the PS table while printing the publication to a file or to a printer.