Abstract: Provided are a computer program product, system, and method for managing cache segments between a global queue and a plurality of local queues by training a machine learning module. A machine learning module is provided input comprising cache segment management information related to management of segments in the local queues by the processing units and accesses of the global queue to transfer cache segments between the local queues and the global queue to output an optimum number parameter comprising an optimum number of segments to maintain in a local queue and a transfer number parameter comprising a number of cache segments to move between a local queue and the global queue. The machine learning module is retrained based on the cache segment management information to output an adjusted transfer number parameter and an adjusted optimum number parameter for the processing units.

Abstract: A computer-implemented method, according to one embodiment, includes: in response to experiencing a loss of data at a first track of a source volume, determining whether a copy of the lost data has been stored at a second track of a target volume. Moreover, in response to determining that a copy of the lost data has been stored at a second track of the target volume, determine whether the copy of the lost data has been altered since being stored at the second track of the target volume. In response to determining that the copy of the lost data has not been altered since being stored at the second track of the target volume, a request for the copy of the lost data is sent to the target volume. In response, the copy of the lost data is received, and used to recover the lost data.

Abstract: Copy source to target operations may be selectively and preemptively undertaken in advance of source destage operations. In another aspect, logic detects sequential writes including large block writes to point-in-time copy sources. In response, destage tasks on the associated point-in-time copy targets are started which include in one embodiment, stride-aligned copy source to target operations which copy unmodified data from the point-in-time copy sources to the point-in-time copy targets in alignment with the strides of the target. As a result, when write data of write operations is destaged to the point-in-time copy sources, such source destages do not need to wait for copy source to target operations since they have already been performed. In addition, the copy source to target operations may be stride-aligned with respect to the stride boundaries of the point-in-time copy targets. Other features and aspects may be realized, depending upon the particular application.

Abstract: A method for improving asynchronous data replication between a primary storage system and a secondary storage system is disclosed. In one embodiment, such a method includes monitoring, in a cache of the primary storage system, unmirrored data elements needing to be mirrored, but that have not yet been mirrored, from the primary storage system to the secondary storage system. The method maintains an LRU list designating an order in which data elements are demoted from the cache. The method determines whether a data element at an LRU end of the LRU list is an unmirrored data element. In the event the data element at the LRU end of the LRU list is an unmirrored data element, the method moves the data element to an MRU end of the LRU list. A corresponding system and computer program product are also disclosed.

Abstract: Provided are a computer program product, system, and method for managing cache segments between a global queue and a plurality of local queues using a machine learning module. Cache segment management information related to management of segments in the local queues and accesses to the global queue to transfer cache segments between the local queues and the global queue, are provided to a machine learning module to output an optimum number parameter comprising an optimum number of segments to maintain in a local queue and a transfer number parameter comprising a number of cache segments to transfer between a local queue and the global queue. The optimum number parameter and the transfer number parameter are sent to a processing unit having a local queue to cause the processing unit to transfer the transfer number parameter of cache segments between the local queue to the global queue.

Abstract: Provided are a computer program product, system, and method for maintaining cache hit ratios for insertion points into a cache list to optimize memory allocation to a cache. A plurality of insertion points to a cache list for the cache each identify a track in the cache list. Insertion points to tracks in the cache list are used to determine locations in the cache list at which to indicate tracks in the cache in the cache list that are to be indicated at the MRU end of the cache list. Indication is made of cache hits for each of the insertion points used to indicate locations in the cache list for tracks accessed while indicated in the cache list. The cache hits indicated for the insertion points are to indicate whether to increase or decrease a size of the cache.

Abstract: Provided are a computer program product, system, and method for detecting potentially malicious code in a host system accessing data from a storage. A trap storage unit is configured for data in the storage and the trap storage unit is indicated as a trap. Storage units are configured for data in the storage that are not indicated as a trap. A request is received to access the trap storage unit from a process executing in a host system. Notification is returned to the host system that the process requesting to access the trap storage unit is a potentially malicious process.

Abstract: Provided are a computer program product, system, and method for selecting resources to make available in local queues for processors to use. Each processor of a plurality of processors maintains a queue of resources for the processor to use when needed for processor operations. One of processors is selected. The selected processor accesses at least one available resource and includes the accessed at least one resource in the queue of the selected processor.

Abstract: Provided are a computer program product, system, and method for invalidating track format information for tracks demoted from cache. Demoted tracks demoted from the cache are indicated in a demoted track list. Track format information is saved for the demoted tracks. The track format information indicates a layout of data in the demoted tracks, wherein the track format information for the demoted tracks is used when the demoted tracks are staged back into the cache. An operation is initiated to invalidate a metadata track of the metadata tracks in the storage. Demoted tracks indicated in the demoted track list having metadata in the metadata track to invalidate are removed. The track format information for the demoted tracks having metadata in the metadata track to invalidate is removed.

Abstract: Provided are techniques for handling cache and Non-Volatile Storage (NVS) out of sync writes. At an end of a write for a cache track of a cache node, a cache node uses cache write statistics for the cache track of the cache node and Non-Volatile Storage (NVS) write statistics for a corresponding NVS track of an NVS node to determine that writes to the cache track and to the corresponding NVS track are out of sync. The cache node sets an out of sync indicator in a cache data control block for the cache track. The cache node sends a message to the NVS node to set an out of sync indicator in an NVS data control block for the corresponding NVS track. The cache node sets the cache track as pinned non-retryable due to the write being out of sync and reports possible data loss to error logs.

Abstract: Provided are a computer program product, system, and method for processing cache miss rates to determine memory space to add to an active cache to reduce a cache miss rate for the active cache. During caching operations to the active cache, information is gathered on an active cache miss rate based on a rate of access to tracks that are not indicated in the active cache list and a cache demote rate. A determination is made as to whether adding additional memory space to the active cache would result in the active cache miss rate being less than the cache demote rate when the active cache miss rate exceeds the cache demote rate. A message is generated indicating to add the additional memory space when adding the additional memory space would result in the active cache miss rate being less than the cache demote rate.

Abstract: Provided are a computer program product, system, and method for queuing prestage requests in one of a plurality of prestage request queues as a function of the number of track holes determined to be present in a track cached in a multi-tier cache. A prestage request when executed prestages read data from storage to a slow cache tier of the multi-tier cache, for one or more sectors identified by one or more track holes. In another aspect, allocated tasks are dispatched to execute prestage requests queued on selected prestage request queues as a function of priority associated with each prestage request queues. Other aspects and advantages are provided, depending upon the particular application.

Abstract: A list of a first type of tracks in a cache is generated. A list of a second type of tracks in the cache is generated, wherein I/O operations are completed relatively faster to the first type of tracks than to the second type of tracks. A determination is made as to whether to demote a track from the list of the first type of tracks or from the list of the second type of tracks.

Abstract: Provided are a computer program product, system, and method for determining an optimum number of threads to make available per core in a multi-core processor complex to execute tasks. A determination is made of a first processing measurement based on threads executing on the cores of the processor chip, wherein each core includes circuitry to independently execute a plurality of threads. A determination is made of a number of threads to execute on the cores based on the first processing measurement. A determination is made of a second processing measurement based on the threads executing on the cores of the processor chip. A determination is made of an adjustment to the determined number of threads to execute based on the second processing measurement resulting in an adjusted number of threads. The adjusted number of threads on the cores is utilized to execute instructions.

Abstract: A method to dynamically switch between data transfer techniques includes receiving an I/O request and computing a cost of executing the I/O request using a memory copy data transfer technique. The memory copy data transfer technique copies cache segments associated with the I/O request from cache memory to a permanently mapped memory, which is permanently mapped to a bus address window. The method also computes a cost of executing the I/O request using a memory mapping data transfer technique. The memory mapping data transfer technique temporarily maps cache segments associated with the I/O request from the cache memory to the bus address window. The method uses one of the memory copy data transfer technique and the memory mapping data transfer technique to transfer cache segments associated with the I/O request, depending on which one is less costly. A corresponding system and computer program product are also disclosed.

Abstract: A method for demoting data from a cache comprising heterogeneous memory types is disclosed. The method maintains, for a data element in the cache, a write access count that is incremented each time the data element is updated in the cache. The cache includes a higher performance portion and a lower performance portion. The method removes the data element from the higher performance portion in accordance with a cache demotion algorithm. If the data element also resides in the lower performance portion and the write access count is below a first threshold, the method leaves the data element in the lower performance portion. If the data element also resides in the lower performance portion and the write access count is at or above the first threshold, the method removes the data element from the lower performance portion. A corresponding system and computer program product are also disclosed.

Abstract: In one embodiment, storage drive dependent track removal processing logic performs destage tasks for tracks cached in a cache as a function of whether the storage drive is classified as a fast class or as slow class of storage drives, for example. In one embodiment, a destage task configured for a slow class storage drive, transfers an entry for a track selected for destaging from a main cache list to a wait cache list to await destaging to the slow class drive. A destage task configured for a fast class storage drive allows the cache list entry for the selected track to remain on the main cache list while the selected track is being destaged to the fast class storage drive, thereby bypassing the transfer of the entry to a wait cache list. Other features and aspects may be realized, depending upon the particular application.

Abstract: A method for storing metadata in a cache comprising heterogeneous memory types is disclosed. The method stages data elements containing metadata into a lower performance portion of a cache. The cache includes the lower performance portion and a higher performance portion. In response to determining that the data elements are updated in the higher performance portion, the method records when the data elements were updated and invalidates the data elements in the lower performance portion. The method scans the lower performance portion for the data elements that are invalidated and re-stages, in the lower performance portion, the data elements that are invalidated and have not been updated in the higher performance portion in a last specified period of time. A corresponding system and computer program product are also disclosed.

Abstract: A method for demoting data from a cache comprising heterogeneous memory types is disclosed. The method maintains for a data element in the cache, a write access count that is incremented each time the data element is updated in the cache. The cache includes a higher performance portion and a lower performance portion. The method also maintains, for the data element, a read access count that is incremented each time a data element is read in the cache. The method removes the data element from the higher performance portion of the cache in accordance with a cache demotion algorithm. If the write access count is below a first threshold and the read access count is above a second threshold, the method places the data element in the lower performance portion. A corresponding system and computer program product are also disclosed.

Abstract: Provided are a method, system, and computer program product in which a storage controller receives a first write command with a first token over a first interface from a host computational device. In response to a failure of the first write command in the storage controller, the storage controller retains selected resources for reuse for a retry of the first write command, wherein the retry of the first write command is expected from the host computational device over a second interface that is a slower communication link than the first interface. In response to receiving, by the storage controller, a second write command with a second token over the second interface, wherein the second token is identical to the first token, the storage controller determines that the second write command is a retry of the first write command and reuses the retained selected resources for executing the second write command.