Patents by Inventor Kevin J. Fischer

Kevin J. Fischer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10593626
    Abstract: A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Ruth A. Brain, Kevin J. Fischer, Michael A. Childs
  • Patent number: 10229879
    Abstract: An embodiment includes a semiconductor structure comprising: a frontend portion including a device layer; a backend portion including a bottom metal layer, a top metal layer, and intermediate metal layers between the bottom and top metal layers; wherein (a) the top metal layer includes a first thickness that is orthogonal to the horizontal plane in which the top metal layer lies, the bottom metal layer includes a second thickness; and the intermediate metal layers includes a third thickness; and (b) the first thickness is greater than or equal to a sum of the second and third thicknesses. Other embodiments are described herein.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Kevin J. Fischer, Christopher M. Pelto, Andrew W. Yeoh
  • Patent number: 9984922
    Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: May 29, 2018
    Assignee: Intel Corporation
    Inventors: Jun He, Kevin J. Fischer, Ying Zhou, Peter K. Moon
  • Publication number: 20180122744
    Abstract: A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.
    Type: Application
    Filed: October 2, 2017
    Publication date: May 3, 2018
    Inventors: Ruth A. BRAIN, Kevin J. FISCHER, Michael A. CHILDS
  • Patent number: 9780038
    Abstract: A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: October 3, 2017
    Assignee: Intel Corporation
    Inventors: Ruth A. Brain, Kevin J. Fischer, Michael A. Childs
  • Patent number: 9627312
    Abstract: An on-chip capacitor a semiconductive substrate is fabricated in a passivation layer that is above the back-end metallization. At least three electrodes are configured in the on-chip capacitor and power and ground vias couple at least two of the at least three electrodes. The first via has a first-coupled configuration to at least one of the first- second- and third electrodes and the second via has a second-coupled configuration to at least one of the first- second- and third electrodes.
    Type: Grant
    Filed: October 1, 2011
    Date of Patent: April 18, 2017
    Assignee: Intel Corporation
    Inventors: Michael A. Childs, Kevin J. Fischer, Sanjay S. Natarajan
  • Publication number: 20170040263
    Abstract: A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.
    Type: Application
    Filed: October 24, 2016
    Publication date: February 9, 2017
    Inventors: Ruth A. Brain, Kevin J. Fischer, Michael A. Childs
  • Publication number: 20170011997
    Abstract: An embodiment includes a semiconductor structure comprising: a frontend portion including a device layer; a backend portion including a bottom metal layer, a top metal layer, and intermediate metal layers between the bottom and top metal layers; wherein (a) the top metal layer includes a first thickness that is orthogonal to the horizontal plane in which the top metal layer lies, the bottom metal layer includes a second thickness; and the intermediate metal layers includes a third thickness; and (b) the first thickness is greater than or equal to a sum of the second and third thicknesses. Other embodiments are described herein.
    Type: Application
    Filed: September 23, 2016
    Publication date: January 12, 2017
    Inventors: Kevin J. Fischer, Christopher M. Pelto, Andrew W. Yeoh
  • Publication number: 20160372366
    Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.
    Type: Application
    Filed: September 1, 2016
    Publication date: December 22, 2016
    Inventors: Jun HE, Kevin J. FISCHER, Ying ZHOU, Peter K. MOON
  • Patent number: 9502281
    Abstract: A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having at least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: November 22, 2016
    Assignee: Intel Corporation
    Inventors: Ruth A. Brain, Kevin J. Fischer, Michael A. Childs
  • Patent number: 9496173
    Abstract: An embodiment includes a semiconductor structure comprising: a frontend portion including a device layer; a backend portion including a bottom metal layer, a top metal layer, and intermediate metal layers between the bottom and top metal layers; wherein (a) the top metal layer includes a first thickness that is orthogonal to the horizontal plane in which the top metal layer lies, the bottom metal layer includes a second thickness; and the intermediate metal layers includes a third thickness; and (b) the first thickness is greater than or equal to a sum of the second and third thicknesses. Other embodiments are described herein.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: November 15, 2016
    Assignee: Intel Corporation
    Inventors: Kevin J. Fischer, Christopher M. Pelto, Andrew W. Yeoh
  • Patent number: 9437545
    Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: September 6, 2016
    Assignee: Intel Corporation
    Inventors: Jun He, Kevin J. Fischer, Ying Zhou, Peter K. Moon
  • Publication number: 20150179562
    Abstract: An embodiment includes a semiconductor structure comprising: a frontend portion including a device layer; a backend portion including a bottom metal layer, a top metal layer, and intermediate metal layers between the bottom and top metal layers; wherein (a) the top metal layer includes a first thickness that is orthogonal to the horizontal plane in which the top metal layer lies, the bottom metal layer includes a second thickness; and the intermediate metal layers includes a third thickness; and (b) the first thickness is greater than or equal to a sum of the second and third thicknesses. Other embodiments are described herein.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 25, 2015
    Inventors: Kevin J. Fischer, Christopher M. Pelto, Andrew W. Yeoh
  • Publication number: 20150097292
    Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.
    Type: Application
    Filed: December 12, 2014
    Publication date: April 9, 2015
    Inventors: Jun HE, Kevin J. FISCHER, Ying ZHOU, Peter K. MOON
  • Patent number: 8996471
    Abstract: A method and apparatus are provided for displaying help content corresponding to the occurrence of an event occurring within a computer. An alert help data file is periodically downloaded at a client computer. When a program alert occurs within a client computer, the alert help data file is searched to identify help content corresponding to the particular occurrence of the alert. An alert identifier may be uniquely assigned to each alert to assist in locating the corresponding help content. Moreover, an assert tag and a function result value may also be utilized to define and locate particular help content. Once located, the help content may be displayed to a user.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: March 31, 2015
    Assignee: Microsoft Corporation
    Inventors: Steven M. Greenberg, Jeffrey E. Larsson, Kevin J. Fischer
  • Patent number: D851062
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: June 11, 2019
    Assignee: Dolby Laboratories Licensing Corporation
    Inventors: Lucas E. Saule, Vincent Voron, Peter Michaelian, Guangyu Jin, Kevin J. Kilpatrick, Branko Lukic, Steven Ryutaro Takayama, Grayson H. Byrd, Adam Scott Koniak, Ariel Laurent Fischer, Robert Edward Borchers
  • Patent number: D857655
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: August 27, 2019
    Assignee: Dolby Laboratories Licensing Corporation
    Inventors: Lucas E. Saule, Vincent Voron, Peter Michaelian, Guangyu Jin, Kevin J. Kilpatrick, Branko Lukic, Steven Ryutaro Takayama, Grayson H. Byrd, Adam Scott Koniak, Ariel Laurent Fischer, Robert Edward Borchers
  • Patent number: D858481
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: September 3, 2019
    Assignee: Dolby Laboratories Licensing Corporation
    Inventors: Lucas E. Saule, Vincent Voron, Peter Michaelian, Guangyu Jin, Kevin J. Kilpatrick, Branko Lukic, Steven Ryutaro Takayama, Grayson H. Byrd, Adam Scott Koniak, Ariel Laurent Fischer, Robert Edward Borchers
  • Patent number: D871368
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: December 31, 2019
    Assignee: Dolby Laboratories Licensing Corporation
    Inventors: Lucas E. Saule, Vincent Voron, Peter Michaelian, Guangyu Jin, Kevin J. Kilpatrick, Branko Lukic, Steven Ryutaro Takayama, Grayson H. Byrd, Adam Scott Koniak, Ariel Laurent Fischer, Robert Edward Borchers
  • Patent number: D872049
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: January 7, 2020
    Assignee: Dolby Laboratories Licensing Corporation
    Inventors: Lucas E. Saule, Vincent Voron, Peter Michaelian, Guangyu Jin, Kevin J. Kilpatrick, Branko Lukic, Steven Ryutaro Takayama, Grayson H. Byrd, Adam Scott Koniak, Ariel Laurent Fischer, Robert Edward Borchers