Patents by Inventor Kevin J. Torek

Kevin J. Torek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6576557
    Abstract: The invention includes a semiconductor processing method in which a semiconductor substrate is exposed to reactive ion etching conditions. The reactive ion etching conditions comprise subjecting exposed surfaces of the substrate to a gas having components therein which are reactive with the exposed surfaces. A total concentration of the reactive components within the gas is less than 4.5%, by volume. In particular aspects, the total concentration of the reactive components can be less than 2% by volume, or less than 1% by volume. Exemplary reactive components are fluorine-containing components, such as NF3.
    Type: Grant
    Filed: May 7, 2002
    Date of Patent: June 10, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Kevin J. Torek, Satish Bedge
  • Patent number: 6562726
    Abstract: A method for removing organometallic and organosilicate residues remaining after a dry etch process from semiconductor substrates. The substrate is exposed to a conditioning solution of a fluorine source, a non-aqueous solvent, a complementary acid, and a surface passivation agent. The fluorine source is typically hydrofluoric acid. The non-aqueous solvent is typically a polyhydric alcohol such as propylene glycol. The complementary acid is typically either phosphoric acid or hydrochloric acid. The surface passivation agent is typically a carboxylic acid such as citric acid. Exposing the substrate to the conditioning solution removes the remaining dry etch residues while minimizing removal of material from desired substrate features.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: May 13, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Kevin J. Torek, Donald L. Yates
  • Patent number: 6541391
    Abstract: The invention includes a semiconductor processing method of cleaning a surface of a copper-containing material by exposing the surface to a mixture having a basic pH and comprising Cl−, NO3− and F−. The invention also includes a semiconductor processing method of forming an opening to a copper-containing substrate. Initially, a mass is formed over the copper-containing substrate. The mass comprises at least one of a silicon nitride and a silicon oxide. An opening is etched through the mass and to the copper-containing substrate. A surface of the copper-containing substrate defines a base of the opening, and is referred to as a base surface. The base surface of the copper-containing substrate is at least partially covered by at least one of a copper oxide, a silicon oxide or a copper fluoride.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: April 1, 2003
    Assignee: Micron Technology, Inc.
    Inventors: David Smith, Kevin J. Torek, Paul A. Morgan
  • Patent number: 6517738
    Abstract: A method for removing organometallic and organosihicate residues remaining after a dry etch process from semiconductor substrates. The substrate is exposed to a conditioning solution of phosphoric acid, hydrofluoric acid, and a carboxylic acid, such as acetic acid, which removes the remaining dry etch residues while minimizing removal of material from desired substrate features. The approximate proportions of the conditioning solution are typically 80 to 95 percent acetic acid, 1 to 15 percent phosphoric acid, and 0.01 to 5.0 percent hydrofluoric acid.
    Type: Grant
    Filed: August 2, 2000
    Date of Patent: February 11, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Kevin J. Torek, Donald L. Yates
  • Patent number: 6453914
    Abstract: A method for removing organometallic and organosilicate residues remaining after a dry etch process from semiconductor substrates. The substrate is exposed to a conditioning solution of phosphoric acid, hydrofluoric acid, and a carboxylic acid, such as acetic acid, which removes the remaining dry etch residues while minimizing removal of material from desired substrate features. The approximate proportions of the conditioning solution are typically 80 to 95 percent acetic acid, 1 to 15 percent phosphoric acid, and 0.01 to 5.0 percent hydrofluoric acid.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: September 24, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Kevin J. Torek, Donald L. Yates
  • Publication number: 20020119656
    Abstract: The invention includes a semiconductor processing method of cleaning a surface of a copper-containing material by exposing the surface to a mixture having a basic pH and comprising Cl−, NO3− and F−. The invention also includes a semiconductor processing method of forming an opening to a copper-containing substrate. Initially, a mass is formed over the copper-containing substrate. The mass comprises at least one of a silicon nitride and a silicon oxide. An opening is etched through the mass and to the copper-containing substrate. A surface of the copper-containing substrate defines a base of the opening, and is referred to as a base surface. The base surface of the copper-containing substrate is at least partially covered by at least one of a copper oxide, a silicon oxide or a copper fluoride.
    Type: Application
    Filed: February 28, 2001
    Publication date: August 29, 2002
    Inventors: David Smith, Kevin J. Torek, Paul A. Morgan
  • Patent number: 6372657
    Abstract: An improved dry plasma cleaning process for the removal of native oxides, or other oxide films or growth residue, from openings formed in an insulating layer provided over a semiconductor substrate, without damaging the substrate or significantly affecting the critical dimension of the opening is disclosed. A mixture of nitrogen trifluoride (NF3), ammonia (NH3) and oxygen (O2) is first injected upstream into a microwave plasma source and is exited, and then the plasma is flowed downstream from the plasma source into a reaction chamber containing the substrate.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: April 16, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Max F. Hineman, Kevin J. Torek
  • Patent number: 6350547
    Abstract: A process of growing silicon oxide to a highly calibrated thickness is provided. In one embodiment, a silicon precursor material is deposited to a first thickness on a substrate, such as a fused glass substrate used for forming microlithography masks. The precursor material is then selectively exposed to ionization and the non-ionized portions of the precursor material are then selectively etched leaving only the implanted portion of the precursor material of the first thickness. The implanted material is then oxidized resulting in an oxide structure having a thickness that is directly correlated to the initial thickness and the coefficient of oxidation. In one embodiment, a selective etch, such as TMAH, is used to remove unimplanted silicon which results in less than one percent etching of the implanted silicon.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: February 26, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Kevin J. Torek
  • Publication number: 20010051440
    Abstract: A method for removing organometallic and organosilicate residues remaining after a dry etch process from semiconductor substrates. The substrate is exposed to a conditioning solution of phosphoric acid, hydrofluoric acid, and a carboxylic acid, such as acetic acid, which removes the remaining dry etch residues while minimizing removal of material from desired substrate features. The approximate proportions of the conditioning solution are typically 80 to 95 percent acetic acid, 1 to 15 percent phosphoric acid, and 0.01 to 5.0 percent hydrofluoric acid.
    Type: Application
    Filed: June 29, 1999
    Publication date: December 13, 2001
    Inventors: KEVIN J. TOREK, DONALD L. YATES
  • Publication number: 20010037816
    Abstract: An apparatus and method for delivering ozone to a workpiece. In one embodiment, fluid is sprayed onto a workpiece placed in an ozone-rich environment. Alternatively, ozone is mixed with the fluid prior to spraying the fluid onto the workpiece. When spraying the fluid, the invention pulses the fluid at desired rates to create a substantially uniform layer of ozone-rich fluid on the workpiece. In another embodiment, the workpiece is also slowly rotated during at least a portion of the time the layer of ozone-rich fluid is applied to the workpiece.
    Type: Application
    Filed: May 25, 2001
    Publication date: November 8, 2001
    Inventors: Kevin J. Torek, Jonathan C. Morgan, Paul A. Morgan
  • Patent number: 6232232
    Abstract: An organic acid/fluoride-containing solution etchant having high selectivity for BPSG to TEOS. In an exemplary situation, a TEOS layer may be used to prevent contamination of other components in a semiconductor device by the boron and phosphorous in a layer of BPSG deposited over the TEOS layer. The etchant of the present invention may be used to etch desired areas in the BPSG layer, wherein the high selectivity for BPSG to TEOS of etchant would result in the TEOS layer acting as an etch stop. A second etch with a known etchant may be utilized to etch the TEOS layer. The known etchant for the second etch can be less aggressive and, thus, not damage the components underlying the TEOS layer.
    Type: Grant
    Filed: April 7, 1998
    Date of Patent: May 15, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Whonchee Lee, Kevin J. Torek
  • Patent number: 6194286
    Abstract: The invention comprises processing deposited oxide and grown oxide materials. In one implementation, a substrate is provided to have outwardly exposed grown oxide material and having deposited oxide material. The grown oxide material is etched substantially selective relative to the deposited oxide material. In another considered aspect, a silicon surface is thermally oxidized to form substantially undoped silicon dioxide over a substrate. A substantially undoped silicon dioxide layer is chemical vapor deposited over the substrate, with at least some of the thermally grown silicon dioxide being outwardly exposed. The exposed thermally grown silicon dioxide layer is vapor etched substantially selective relative to the deposited silicon dioxide layer using an etch chemistry comprising substantially anhydrous HF and an organic primer.
    Type: Grant
    Filed: January 17, 2000
    Date of Patent: February 27, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Kevin J. Torek
  • Patent number: 6165853
    Abstract: A method of forming trench isolated integrated circuitry on a substrate provides a substrate having a first insulating material within and projecting from an isolation trench and a second insulating material laterally proximate the first insulating material. The second insulating material is etched substantially selective relative to the first insulating material to expose substrate beneath the second insulating material. After the etching, a gate dielectric layer is formed over the exposed substrate. A transistor gate is formed over the gate dielectric layer. In but one other implementation, an oxide layer is thermally grown over a semiconductive substrate. An isolation trench is formed through the thermal oxide layer and the semiconductive substrate. Oxide is deposited within the trenches and formed to project outwardly relative to the thermal oxide.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: December 26, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Michael Nuttall, Kevin J. Torek, David L. Chapek
  • Patent number: 6150277
    Abstract: A process of growing silicon oxide to a highly calibrated thickness is provided. In one embodiment, a silicon precursor material is deposited to a first thickness on a substrate, such as a fused glass substrate used for forming microlithography masks. The precursor material is then selectively exposed to ionization and the non-ionized portions of the precursor material are then selectively etched leaving only the implanted portion of the precursor material of the first thickness. The implanted material is then oxidized resulting in an oxide structure having a thickness that is directly correlated to the initial thickness and the coefficient of oxidation. In one embodiment, a selective etch, such as TMAH, is used to remove unimplanted silicon which results in less than one percent etching of the implanted silicon.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: November 21, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Kevin J. Torek
  • Patent number: 6090683
    Abstract: The invention comprises processing deposited oxide and grown oxide materials. In one implementation, a substrate is provided to have outwardly exposed grown oxide material and having deposited oxide material. The grown oxide material is etched substantially selective relative to the deposited oxide material. In another considered aspect, a silicon surface is thermally oxidized to form substantially undoped silicon dioxide over a substrate. A substantially undoped silicon dioxide layer is chemical vapor deposited over the substrate, with at least some of the thermally grown silicon dioxide being outwardly exposed. The exposed thermally grown silicon dioxide layer is vapor etched substantially selective relative to the deposited silicon dioxide layer using an etch chemistry comprising substantially anhydrous HF and an organic primer.
    Type: Grant
    Filed: June 16, 1997
    Date of Patent: July 18, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Kevin J. Torek
  • Patent number: 6087273
    Abstract: An improved wet etchant process is provided which has greater selectivity than existing hot phosphoric acid etching processes and which maintains a high etch rate in use. The etchant composition includes a second acid having a boiling point higher than that of the phosphoric acid.
    Type: Grant
    Filed: January 25, 1999
    Date of Patent: July 11, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Kevin J. Torek, Whonchee Lee
  • Patent number: 5885903
    Abstract: An improved wet etchant process is provided which has greater selectivity than existing hot phosphoric acid etching processes and which maintains a high etch rate in use. The etchant composition includes a second acid having a boiling point higher than that of the phosphoric acid.
    Type: Grant
    Filed: January 22, 1997
    Date of Patent: March 23, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Kevin J. Torek, Whonchee Lee