Patents by Inventor Kevin John Nowka
Kevin John Nowka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9076509Abstract: Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.Type: GrantFiled: July 29, 2009Date of Patent: July 7, 2015Assignee: International Business Machines CorporationInventors: Ching-Te Kent Chuang, Keunwoo Kim, Jente Benedict Kuang, Hung Cai Ngo, Kevin John Nowka
-
Patent number: 8010066Abstract: A digital transmission circuit and interface provide selectable power consumption via multiple weighted driver slices, improving the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.Type: GrantFiled: February 1, 2008Date of Patent: August 30, 2011Assignee: International Business Machines CorporationInventors: Juan-Antonio Carballo, Kevin John Nowka, Ivan Vo, Seung-moon Yoo
-
Patent number: 7952422Abstract: Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.Type: GrantFiled: July 29, 2009Date of Patent: May 31, 2011Assignee: International Business Machines CorporationInventors: Ching-Te Chuang, Keunwoo Kim, Jente Benedict Kuang, Hung Cai Ngo, Kevin John Nowka
-
Patent number: 7876131Abstract: A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.Type: GrantFiled: September 21, 2007Date of Patent: January 25, 2011Assignee: International Business Machines CorporationInventors: Ching-Te Chuang, Keunwoo Kim, Jente Benedict Kuang, Kevin John Nowka
-
Patent number: 7636556Abstract: A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing power consumption when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.Type: GrantFiled: January 16, 2008Date of Patent: December 22, 2009Assignee: International Business Machines CorporaionInventors: Juan-Antonio Carballo, Kevin John Nowka, Ivan Vo, Seung-moon Yoo
-
Publication number: 20090302929Abstract: Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.Type: ApplicationFiled: July 29, 2009Publication date: December 10, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ching-Te Kent Chuang, Keunwoo Kim, Jente Benedict Kuang, Hung Cai Ngo, Kevin John Nowka
-
Publication number: 20090303778Abstract: Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.Type: ApplicationFiled: July 29, 2009Publication date: December 10, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ching-Te Kent Chuang, Keunwoo Kim, Jente Benedict Kuang, Hung Cai Ngo, Kevin John Nowka
-
Publication number: 20090302894Abstract: A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.Type: ApplicationFiled: September 21, 2007Publication date: December 10, 2009Applicant: International Business Machines CorporationInventors: Ching-Te Chuang, Keunwoo Kim, Jente Benedict Kuang, Kevin John Nowka
-
Patent number: 7522670Abstract: A digital transmission circuit and method providing selectable power consumption via single-ended or differential operation improves the flexibility of an interface while reducing power consumption when possible. A differential path is provided through the transmitter output driver stages and portions are selectively disabled when the transmission circuit is in a lower-power operating mode. A single-ended to differential converter circuit can be used to construct a differential signal for output to the final driver stage. The selection of power mode can be made via feedback from a channel quality measurement unit or may be hardwired or selected under programmatic control. The longer delay or skew of the lower-power single-ended mode is compensated for by the relaxed requirements of the channel when conditions permit the use of the lower-power single-ended mode.Type: GrantFiled: February 3, 2005Date of Patent: April 21, 2009Assignee: International Business Machines CorporationInventors: Juan-Antonio Carballo, Kevin John Nowka, Ivan Vo, Seung-moon Yoo
-
Patent number: 7443195Abstract: A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.Type: GrantFiled: February 9, 2004Date of Patent: October 28, 2008Assignee: International Business Machines CorporationInventors: Juan-Antonio Carballo, Jeffrey L. Burns, Gary Dale Carpenter, Kevin John Nowka, Ivan Vo, Seung-moon Yoo
-
Publication number: 20080125062Abstract: A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing power consumption when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.Type: ApplicationFiled: January 16, 2008Publication date: May 29, 2008Inventors: Juan-Antonio Carballo, Kevin John Nowka, Ivan Vo, Seung-moon Yoo
-
Publication number: 20080125063Abstract: A digital transmission circuit and interface provide selectable power consumption via multiple weighted driver slices, improving the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.Type: ApplicationFiled: February 1, 2008Publication date: May 29, 2008Inventors: Juan-Antonio Carballo, Kevin John Nowka, Ivan Vo, Seung-moon Yoo
-
Patent number: 7353007Abstract: A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.Type: GrantFiled: February 3, 2005Date of Patent: April 1, 2008Assignee: International Business Machines CorporationInventors: Juan-Antonio Carballo, Kevin John Nowka, Ivan Vo, Seung-moon Yoo
-
Patent number: 7336105Abstract: A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.Type: GrantFiled: June 28, 2005Date of Patent: February 26, 2008Assignee: International Business Machines CorporationInventors: Ching-Te Chuang, Keunwoo Kim, Jente Benedict Kuang, Kevin John Nowka
-
Patent number: 7265589Abstract: A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an evaluate phase of the clock signal in response to a Boolean combination of the logic inputs. The logic tree has a stacked configuration with at least one multi-gate FEAT device for coupling an intermediate node of the logic tree to the dynamic node in response to a first logic input of the plurality of logic inputs or in response to the pre-charge phase of the clock signal. The multi-gate FEAT device has one gate coupled to the first logic input and a second gate coupled to a complement of the clock signal used to pre-charge the dynamic node.Type: GrantFiled: June 28, 2005Date of Patent: September 4, 2007Assignee: International Business Machines CorporationInventors: Ching-Te Chuang, Keunwoo Kim, Jente Benedict Kuang, Kevin John Nowka
-
Patent number: 7219244Abstract: A single-stage level shifting circuit is used to interface control signals across the boundary between voltage domains with differing positive or ground voltage potentials Asserted states are determined by the difference between the positive voltages potentials and the ground potentials. A lower positive power supply potential is not used to turn OFF PFET coupled to a higher positive power supply potential. Likewise a higher ground power supply potential is not used to turn OF NFETs coupled to a power domain where is significant ground shift. The single stage level shifting circuit has keeper devices that hold asserted states using voltages within the power gated domain.Type: GrantFiled: August 25, 2005Date of Patent: May 15, 2007Assignee: International Business Machines CorporationInventors: Jente Benedict Kuang, Hung C. Ngo, Kevin John Nowka
-
Patent number: 7142015Abstract: A buffer, logic circuit, and data processing system employing fast turn-off drive circuitry for reducing leakage. Leakage current in logic circuitry is managed by coupling and decoupling the voltage potentials applied to large, high-leakage devices. Circuitry includes a low leakage logic path for holding logic states of an output after turning off high-leakage devices. A fast turn-off logic path in parallel with the low leakage logic path is used to assert each logic state in the forward direction from input to output. The large output device in each fast turn-off path is relieved of leakage stress by asserting logic states at driver inputs that cause the driver to turn OFF after the output logic state has been asserted.Type: GrantFiled: September 23, 2004Date of Patent: November 28, 2006Assignee: International Business Machines CorporationInventors: Jente Benedict Kuang, Hung Cai Ngo, Kevin John Nowka
-
Patent number: 7088141Abstract: A multi-threshold complementary metal-oxide semiconductor (MTCMO) bus circuit reduces bus power consumption via a reduced circuit leakage standby and pulsed control of standby mode so that the advantages of MTCMOS repeater design are realized in dynamic operation. A pulse generator pulses the high-threshold voltage power supply rail standby switching devices in response to changes detected at the bus circuit inputs. The delay penalty associated with leaving the standby mode is overcome by reducing cross-talk induced delay via a cross-talk noise minimization encoding and decoding scheme. A subgroup of bus wires is encoded and decoded, simplifying the encoding, decoding and change detection logic and results in the bus subgroup being taken out of standby mode only when changes occur in one or more of the subgroup inputs, further reducing the power consumption of the overall bus circuit.Type: GrantFiled: October 14, 2004Date of Patent: August 8, 2006Assignee: International Business Machines CorporationInventors: Harmander Singh Deogun, Kevin John Nowka, Rahul M. Rao
-
Patent number: 6836849Abstract: A method and controller for managing power and performance of a multiprocessor (MP) system is described. The controller receives sensor data corresponding to physical parameters within the MP system. The controller also receives quality of service and policy parameters corresponding to the MP system. The quality of service parameters define commitments to customers for utilization of the MP system. The policy parameters correspond to operation limits on inputs and outputs of the MP system. The operation input limits relate to the cost and availability of power or individual processor availability. The operation output limits relate to the amount of heat, acoustic noise levels, EMC levels, etc. that the individual or group of processors in the MP system are allowed to generate in a particular environment. A controller receives the physical parameters, the quality of service parameters and policy parameters and determines performance goals for the MP system and processors within the MP system.Type: GrantFiled: April 5, 2001Date of Patent: December 28, 2004Assignee: International Business Machines CorporationInventors: Bishop Chapman Brock, Harm Peter Hofstee, Mark A. Johnson, Thomas Walter Keller, Jr., Kevin John Nowka
-
Patent number: 6812739Abstract: A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.Type: GrantFiled: September 26, 2002Date of Patent: November 2, 2004Assignee: International Business Machines CorporationInventors: Juan-Antonio Carballo, Jeffrey L. Burns, Gary Dale Carpenter, Kevin John Nowka, Ivan Vo, Seung-moon Yoo