Abstract: A method and system for designing electronic devices by encouraging reuse as a design principle and rewarding both the design of reusable components as well as the subsequent reuse of such components. Typically, a design team evaluates each component in a proposed device for its potential to be implemented with a previously designed component. If a decision is made to forego previously designed components, the design team is encouraged to incorporate re-usability principles into the component design by a reward or compensation structure that rewards both the individual members of a team as well as the corporate entity to which the design team is assigned. The reward structure also encourages teams to use existing designs wherever possible by rewarding a team that reuses an existing component. An innovation administrator may adjust the relative rewards for incorporating reusability into a design vs. reusing a design to effect a preference for innovation in selected areas.

Abstract: The Sync State outputs are used in combination with the multiple phase outputs to generate and error signal which is operable to generate voltage which controls the frequency of the MVCO and to generate a shifted clock which is divided in a sequential circuit to generate the quadrature clock with a frequency F.

Abstract: A method and controller for managing power and performance of a multiprocessor (MP) system is described. The controller receives sensor data corresponding to physical parameters within the MP system. The controller also receives quality of service and policy parameters corresponding to the MP system. The quality of service parameters define commitments to customers for utilization of the MP system. The policy parameters correspond to operation limits on inputs and outputs of the MP system. The operation input limits relate to the cost and availability of power or individual processor availability. The operation output limits relate to the amount of heat, acoustic noise levels, EMC levels, etc. that the individual or group of processors in the MP system are allowed to generate in a particular environment. A controller receives the physical parameters, the quality of service parameters and policy parameters and determines performance goals for the MP system and processors within the MP system.

Abstract: A reference clock of frequency F is used to generate a quadrature clock at the same frequency F without generating frequencies higher than F. A multiphase voltage-controlled oscillator (MVCO) has a nominal frequency less than F is used in a feedback circuit with a multiple phase (MP) phase detector that which operates on the multiple phases of the MVCO. The multiple phases of the MVCO are sampled at and latched on both edges of the reference clock to generate phase detector outputs which are combined in combinational logic to generate Sync State outputs. The Sync State outputs are used in combination with the multiple phase outputs to generate an error signal with is operable to generate a control voltage which controls the frequency of the MVCO and to generate a shifted clock which is divided in a sequential circuit to generate the quadrature clock with a frequency F.

Abstract: An edge-triggered latch that incorporates pass-transistor logic (PTL) in the data and clock generation paths. In accordance with one embodiment, an edge-triggered latch includes a data input and at least one data path PTL transistor that passes data from the data input into a storage node in response to a latch trigger signal. A latch trigger circuit generates the latch-trigger signal in response to a clock signal transition.

Abstract: An edge-triggered latch that incorporates pass-transistor logic (PTL) in the data and clock generation paths. In accordance with one embodiment, an edge-triggered latch includes a data input and at least one data path PTL transistor that passes data from the data input into a storage node in response to a latch trigger signal. A latch trigger circuit generates the latch-trigger signal in response to a clock signal transition.

Abstract: The Sync State outputs are used in combination with the multiple phase outputs to generate and error signal which is operable to generate a control voltage which controls the frequency of the MVCO and to-generate a shifted clock which is divided in a sequential circuit to generate the quadrature clock with a frequency F.

Abstract: An apparatus for rounding intermediate normalized mantissas within a floating-point processor is disclosed. The apparatus for rounding intermediate normalized mantissas within a floating-point processor includes an AND circuit, a selection circuit, and a multiplexor. The AND circuit generates an AND signal and its complement from a normalized mantissa. The selection circuit generates a select_AND signal and its complement from the normalized mantissa. The multiplexor, which is coupled to the AND circuit and the selection circuit, chooses either the AND signal or its complement signal as a rounded normalized mantissa according to the select_AND signal and its complement signal from the selection circuit.

Abstract: A zero/one anticipator having an integrated sign selector is disclosed. A leading zeros string and a leading ones string are generated by examining carry propagates, generates, and kills of two adjacent bits of two input operands to an adder within a floating-point processor. The leading zeros string is for a positive sum, and the leading ones string is for a negative sum. A normalization shift amount is then determined from the leading zeros string and the leading ones string. A sign of a sum of the two input operands is then determined separately but concurrently with the normalization shift amount determination process. The sign is then utilized to select either the positive sum or the negative sum for a proper normalization shift amount.

Abstract: A 6-to-3 carry-save binary adder is disclosed. The 6-to-3 carry-save adder includes a means for receiving six data inputs and a means for simultaneously adding the six data inputs to generate a first data output, a second data output, and a third data output. The first data output is a SUM output, the second data output is a CARRY—2 output, and the third data output is a CARRY—4 output.

Abstract: A method and apparatus for selectable word line boosting in a memory device provides operating of the memory device over wide power supply ranges. A voltage reference and a comparator determine whether or not the power supply voltage has dropped below the range in which word line boosting is not required. If the power supply voltage has dropped, word line boosting is enabled, improving the noise margin and access time of the memory when operating at lower voltages.

Abstract: A method and apparatus for adjusting time delays in circuits with multiple operating supply voltages are disclosed. A voltage level detector and a delay means are coupled to a critical timing circuit of an integrated circuit capable of operating at multiple supply voltages. The voltage level detector detects a supply voltage at which the integrated circuit is operating. When the operating supply voltage of the integrated circuit changes from a first voltage level to a second voltage level, the voltage level detector sends a signal to the delay means and to a current enhancement circuit such that the delay means and current enhancement circuit can automatically modify the delay of the switching time of an output signal from the critical timing circuit.

Abstract: A low latency fused multiply-adder for adding a product of a first binary number and a second binary number to a third binary number is disclosed. The low latency fused multiply-adder includes a partial product generation module, a partial product reduction module, and a carry propagate adder. The partial product generation module generates a set of partial products from the first binary number and the second binary number. Coupled to the partial product generation module, the partial product reduction module combines the set of partial products with the third binary number to produce a redundant Sum and a redundant Carry. Finally, the carry propagate adder adds the redundant Sum and the redundant Carry to yield a Sum Total.

Abstract: A processor includes execution resources and condition code logic. The execution resources execute an arithmetic or logical instruction by arithmetically or logically combining at least two operands. Concurrent with the execution of the arithmetic or logical instruction by the execution resources, the condition code logic determines less than, greater than, and equal to condition code bits associated with the result of the arithmetic or logical instruction. In one embodiment, the condition code logic includes a single computation stage that receives as inputs individual bit values of bit positions within first and second operands and logically combines the individual bit values. The single computation stage outputs, for each bit position, propagate, generate, and kill signals that collectively indicate values for the less than, greater than, and equal to condition code bits.

Abstract: A method for providing a through wafer connection to an integrated circuit silicon package. A hole is first created in the silicon package with an inner surface area extending from the bottom surface of the silicon package to the top surface of the silicon package. The hole is created by one of two methods. The first involves mechanical drilling with a diamond bit rotated at a high rate of speed. The second involves ultrasonically milling utilizing a slurry and steel fingers. The inner surface area of the hole is covered with an insulating material to insulate the conductive material which is later deposited and to serve as a diffusion barrier, then a seed material is placed in the hole. Finally, the hole is filled with a conductive material which is utilized to provide large power inputs or signaling connections to the integrated circuit chips.

Abstract: A superscalar computer architecture for executing instructions out-of-order, comprising a multiplicity of execution units, a plurality of registers, and a register renaming circuit which generates a list of tags corresponding to specific registers that are not in use during loading of a given instruction. A table is constructed having one bit for each register per instruction in flight. The entries in the table may be combined in a logical OR fashion to create a vector that identifies which registers are in use by instructions that are in flight. Validity bits can also be generated to indicate validity of the generated tags, wherein a generated tag is invalid only if an insufficient number of registers are available during loading of the given instruction. The execution units are preferably pipelined.

Abstract: A method for anticipating leading zeros/ones in a floating-point processor is disclosed. A leading zeros string and a leading ones string is generated by examining carry propagates, generates, and kills of two adjacent bits of two input operands to an adder within a floating-point processor. The leading zeros string is for a positive sum, and the leading ones string is for a negative sum. A normalization shift amount is calculated directly and concurrently from the leading zeros string and the leading ones strings prior to a determination of a sign of an output of the positive sum and the negative sum.

Abstract: A high-speed carry-lookahead binary adder is disclosed. The binary adder includes multiple rows of carry-lookahead circuits, a half-sum module, and a sum/carry module. A first carry-lookahead circuit row includes multiple eight-bit group generate circuits and multiple eight-bit group propagate circuits. Each of the eight-bit group generate circuits produces a generate signal for a corresponding bit location. Each of the eight-bit group propagate circuits produces a propagate signal for a corresponding bit location. The half-sum module is utilized to generate a half-sum signal. By utilizing the half-sum signal, the generate signals, and the propagate signals, the sum/carry module generates sum signals and a carry signal.

Abstract: A silicon wafer is etched to form a first and second series of guidance features. The features of the first series are larger than and surround the features of the second series. The second series is clustered into groups and a hole is formed in the center of each group. The wafer is designed to integrate a silicon package having preformed contacts with a plurality of silicon-based chips. The package and each chip has a series of guidance recesses which correspond to the guidance features of the first and second series, respectively. One chip is placed on top of each group of the second series, and the package is placed on top of the first series. The recesses in the package and chips will precisely align with and slidingly engage the upper ends of the features. Since the features of the first series are larger than those of the second series, there is a clearance between the package and the chips.

Abstract: A processor includes at least an execution unit that executes an instruction by performing an operation indicated by the instruction utilizing one or more operands and condition code logic that determines less than, greater than, and equal to condition code bits associated with the instruction concurrently with execution of the instruction by the execution unit. In one embodiment, the condition code logic includes a single computation stage that receives as inputs individual bit values of bit positions within first and second operands and logically combines the individual bit values. The single computation stage outputs, for each bit position, propagate, generate, and kill signals that collectively indicate values for the less than, greater than, and equal to condition code bits. One or more merging stages coupled to the computation stage then merge the propagate, generate, and kill signals into output signals that set the condition code bits.