Abstract: A method and apparatus provide means for saving and restoring processor register values and allocating and deallocating stack memory. A first field of a save instruction encodes whether a value in a register of a processor is saved as an argument value or a static value. A second field of the save instruction encodes a size of a stack frame created during execution of the save instruction. An argument value is saved in a calling program's stack frame. A static value is saved in a called program's stack frame. A restore instruction is used to restore static values and deallocate the stack frame. The save and restore instructions may be executed using any programmable device, including a single instruction set architecture processor or a multi-instruction set architecture processor.

Abstract: A shared resource access control system having a gating storage responsive to a plurality of controls with each of the controls derived from an instruction context identifying the shared resource, the gating storage including a plurality of sets of access method functions with each set of access method functions including a first access method function and a second access method function with the gating storage producing a particular one access method function from a particular one set responsive to the controls; and a controller, coupled to the gating storage, for controlling access to the shared resource using the particular one access method function.

Abstract: A configurable instruction set architecture is provided whereby a single virtual instruction may be used to generate a sequence of instructions. Dynamic parameter substitution may be used to substitute parameters specified by a virtual instruction into instructions within a virtual instruction sequence.

Abstract: a multiprocessing system, including a multithreading microprocessor and a multiprocessor operating system (OS), is disclosed. The microprocessor includes a plurality of thread contexts (TCs) configured as an array, each having a program counter, a general purpose register set for executing a thread, and a register for storing an index of the respective TC within the array. The OS maintains a table of entries, each the entry for storing a CPU-unique value for a respective one of the TCs. The OS comprises a respective thread configured to execute on each of the respective TCs and to read the index from the register of the respective one of the TCs and to read the respective CPU-unique value for the respective one of the TCs using the index.

Abstract: A multiprocessing system, including a multithreading microprocessor and a multiprocessor operating system (OS), is disclosed. The microprocessor includes a plurality of thread contexts (TCs), each having a program counter and a general purpose register set for executing a thread. The microprocessor also includes a translation lookaside buffer (TLB), shared by the plurality of TCs rather than being replicated for each of the plurality of TCs, and privileged to be managed only by operating system-privileged threads rather than by user-privileged threads. The OS manages the TLB, and schedules execution of both the operating system-privileged threads and the user-privileged threads on the plurality of TCs.

Abstract: A multiprocessing system including a multithreading microprocessor and multiprocessor operating system (OS) is disclosed. The microprocessor includes a first and a second plurality of thread contexts (TCs), each TC having a program counter and a general purpose register set for executing a thread. The microprocessor also includes a first and a second shared privileged resource, shared by the first and second respective plurality of TCs rather than being replicated for each of the respective first and second plurality of TCs, and privileged to be managed only by operating system-privileged threads rather than by user-privileged threads. The OS manages the first and second shared privileged resource and schedules execution of both the operating system-privileged threads and the user-privileged threads on the plurality of TCs.

Abstract: A multiprocessing system, including a multithreading microprocessor and a multiprocessor operating system (OS), is disclosed. The microprocessor includes a plurality of thread contexts (TCs), each having a program counter and a general purpose register set for executing a thread. The OS includes a data structure having an entry for each of the plurality of TCs, each entry containing information describing capabilities of the corresponding one of the plurality of TCs. Each entry further comprises a TC identifier field for identifying a corresponding one of the plurality of TCs. The OS populates the TC identifier field for each of the entries with a unique identifier value.

Abstract: A multiprocessing system is disclosed. The system includes a multithreading microprocessor, including a plurality of thread contexts (TCs), each comprising a first control indicator for controlling whether the TC is exempt from servicing interrupt requests to an exception domain for the plurality of TCs, and a virtual processing element (VPE), comprising the exception domain, configured to receive the interrupt requests, wherein the interrupt requests are non-specific to the plurality of TCs, wherein the VPE is configured to select a non-exempt one of the plurality of TCs to service each of the interrupt requests, the VPE further comprising a second control indicator for controlling whether the VPE is enabled to select one of the plurality of TCs to service the interrupt requests.

Abstract: A multiprocessing system is disclosed. The system includes a multithreading microprocessor including a plurality of thread contexts (TCs), each having a program counter and a general purpose register set for executing a thread. The microprocessor also includes a shared privileged resource, shared by the plurality of TCs rather than being replicated for each of the plurality of TCs, and privileged to be managed only by operating system-privileged threads rather than by user-privileged threads. The system also includes a multiprocessor operating system (OS), configured to manage the shared privileged resource, and to schedule execution of both the operating system-privileged threads and the user-privileged threads on the plurality of TCs.

Abstract: A multiprocessing system is disclosed. The system includes a multithreading microprocessor having a plurality of thread contexts (TCs), a translation lookaside buffer (TLB) shared by the plurality of TCs, and an instruction scheduler, coupled to the plurality of TCs, configured to dispatch to execution units, in a multithreaded fashion, instructions of threads executing on the plurality of TCs. The system also includes a multiprocessor operating system (OS), configured to schedule execution of the threads on the plurality of TCs, wherein a thread of the threads executing on one of the plurality of TCs is configured to update the shared TLB, and prior to updating the TLB to disable interrupts, to prevent the OS from unscheduling the TLB-updating thread from executing on the plurality of TCs, and disable the instruction scheduler from dispatching instructions from any of the plurality of TCs except from the one of the plurality of TCs on which the TLB-updating thread is executing.

Abstract: A multiprocessing system is disclosed. The system includes a multithreading microprocessor including a plurality of thread contexts (TCs), each having a program counter and a general purpose register set for executing a thread. The microprocessor also includes a shared privileged resource, shared by the plurality of TCs rather than being replicated for each of the plurality of TCs, and privileged to be managed only by operating system-privileged threads rather than by user-privileged threads. The system also includes a multiprocessor operating system (OS), configured to manage the shared privileged resource, and to schedule execution of both the operating system-privileged threads and the user-privileged threads on the plurality of TCs.

Abstract: A multiprocessing system is disclosed. The system includes a multithreading microprocessor having a plurality of thread contexts (TCs), a translation lookaside buffer (TLB) shared by the plurality of TCs, and an instruction scheduler, coupled to the plurality of TCs, configured to dispatch to execution units, in a multithreaded fashion, instructions of threads executing on the plurality of TCs. The system also includes a multiprocessor operating system (OS), configured to schedule execution of the threads on the plurality of TCs, wherein a thread of the threads executing on one of the plurality of TCs is configured to update the shared TLB, and prior to updating the TLB to disable interrupts, to prevent the OS from unscheduling the TLB-updating thread from executing on the plurality of TCs, and disable the instruction scheduler from dispatching instructions from any of the plurality of TCs except from the one of the plurality of TCs on which the TLB-updating thread is executing.

Abstract: A multiprocessing system is disclosed. The system includes a multithreading microprocessor, including a plurality of thread contexts (TCs), each comprising a first control indicator for controlling whether the TC is exempt from servicing interrupt requests to an exception domain for the plurality of TCs, and a virtual processing element (VPE), comprising the exception domain, configured to receive the interrupt requests, wherein the interrupt requests are non-specific to the plurality of TCs, wherein the VPE is configured to select a non-exempt one of the plurality of TCs to service each of the interrupt requests, the VPE further comprising a second control indicator for controlling whether the VPE is enabled to select one of the plurality of TCs to service the interrupt requests.

Abstract: A bifurcated instruction scheduler for dispatching instructions of multiple threads concurrently executing in a multithreading processor is provided. The scheduler includes a first portion within a reusable core that is not customizable by a customer, a second portion outside the core that is customizable, and an interface coupling the second portion to the core. The second portion implements a thread scheduling policy that may be customized to the customer's particular application. The first portion may be scheduling policy-agnostic and issues instructions of the threads each clock cycle to execution units based on the scheduling policy communicated by the second portion. The second portion communicates the scheduling policy via a priority for each of the threads. When the core commits an instruction for execution, the core communicates to the second portion which thread the committed instruction is in to enable the second portion to update the priorities in response thereto.

Abstract: A multiprocessor computer system includes an exception domain having multiple thread contexts (TCs) each having a restart address register, and a timer that generates a periodic interrupt request to the exception domain. The exception domain selects an eligible TC to service the interrupt request, which is non-specific regarding which TC to select. A first interrupt handler executes on the selected TC to service the interrupt request to schedule a set of processes assigned by the SMP OS for execution on the selected TC, and write an address of a second interrupt handler to the restart address register of each TC other than the selected TC. The second interrupt handler schedules a plurality of sets of processes assigned by the SMP OS for execution on respective ones of the TCs other than the selected TC.

Abstract: A multithreading microprocessor has a plurality of thread contexts (TCs) each including sufficient state, such as general purpose registers and program counter, to execute a separate thread of execution as one of a plurality of symmetric processors controlled by a multiprocessor operating system. However, the microprocessor hardware does not support the ability for one TC to direct an exception to another TC, i.e., to specify to which of the other TCs the exception is directed. A first thread running on a first TC of the operating system executes architected instructions to halt a second thread (either user or kernel thread) running on a second TC, save state of the second TC, write the second TC state to emulate an exception—including writing a restart register with the address of an exception handler, and unhalt the second TC to execute the exception hander.

Abstract: An apparatus and method are provided that disassociates the power consumed by a processing system from the instructions that it executes. The apparatus includes a power predictor that predicts the power that will be consumed by the processing system during execution of particular instructions, and a subsystem inhibition control, that selectively turns on/off available subsystems within the processing system based on the power that is predicted to be consumed. By predicting the power that will be consumed during execution, and by selectively turning on/off particular subsystems, the total power consumed by the processing system can be made invariant, or random. In either case, a counterweight current can be added to the processing system, depending on which of the subsystems are available to be turned on/off, and which are turned on/off, to further disassociate the total power consumed by the processing system from the instructions it is executing.

Abstract: A shared resource access control system having a gating storage responsive to a plurality of controls with each of the controls derived from an instruction context identifying the shared resource, the gating storage including a plurality of sets of access method functions with each set of access method functions including a first access method function and a second access method function with the gating storage producing a particular one access method function from a particular one set responsive to the controls; and a controller, coupled to the gating storage, for controlling access to the shared resource using the particular one access method function.

Abstract: A memory interface for use with a multiprocess memory system having a gating memory, the gating memory associating one or more memory access methods with each of a plurality of memory locations of the memory system wherein the gating memory returns a particular one access method for a particular one memory location responsive to a memory access instruction relating to the particular one memory location, the interface including: a request storage for storing a plurality of concurrent memory access instructions for one or more of the particular memory locations, each the memory access instruction issued from an associated independent thread context; an arbiter, coupled to the request storage, for selecting a particular one of the memory access instructions to apply to the gating memory; and a controller, coupled to the request storage and to the arbiter, for: storing the plurality of memory access instructions in the request storage; initiating application of the particular one memory access instruction selecte

Abstract: A multithreading microprocessor is disclosed. The microprocessor includes a plurality of thread contexts. The microprocessor provides instructions that enable a thread context issuing the instructions to move a value between itself and a target thread context distinct from the issuing thread context independent of cooperation from the target thread context. The instructions employ an operand to specify the target thread context. In one embodiment, the microprocessor is also a virtual multiprocessor including a plurality of virtual processing elements. Each virtual processing element includes a plurality of thread contexts. The instructions also employ a second operand to specify the target virtual processing element.