Abstract: A yield instruction for execution in a multithreaded microprocessor is disclosed. The yield instruction includes an operand. If the operand is zero the microprocessor terminates the program thread including the yield instruction. If the operand is ?1 the microprocessor unconditionally reschedules the program thread. If the operand is a positive integer the microprocessor views the operand as a bit vector specifying one or more yield qualifier inputs, such as interrupt signals, and conditionally reschedules the thread based on the qualifier inputs and bit vector values. The microprocessor also includes a mask register that specifies a bit vector of the qualifier inputs. If the operand specifies a qualifier input not also specified in the mask register, an exception to the instruction is raised. The instruction returns a value specifying the values of the qualifier inputs qualified by the mask register value.

Abstract: Mechanisms for dynamically configuring the resources of a virtual multiprocessor are provided. The invention contemplates provision of an apparatus to configure resources for one or more virtual processing elements in a virtual multiprocessor. The apparatus includes a virtual multiprocessor context, one or more virtual processing element contexts, and configuration logic. The virtual multiprocessor context, prescribes the resources, and controls a configuration state of the virtual multiprocessor. The one or more virtual processing element contexts each exclusively correspond to one of the one or more virtual processing elements. The one or more virtual processing element contexts each have first logic, for prescribing whether the one of the one or more virtual processing elements is permitted to configure the resources; and second logic, for prescribing a subset of the resources that is allocated to said one of the one or more virtual processing elements.

Abstract: A fork instruction for execution on a multithreaded microprocessor and occupying a single instruction issue slot is disclosed. The fork instruction, executing in a parent thread, includes a first operand specifying the initial instruction address of a new thread and a second operand. The microprocessor executes the fork instruction by allocating context for the new thread, copying the first operand to a program counter of the new thread context, copying the second operand to a register of the new thread context, and scheduling the new thread for execution. If no new thread context is free for allocation, the microprocessor raises an exception to the fork instruction. The fork instruction is efficient because it does not copy the parent thread general purpose registers to the new thread. The second operand is typically used as a pointer to a data structure in memory containing initial general purpose register set values for the new thread.

Abstract: A method and apparatus provide means for saving and restoring processor register values and allocating and deallocating stack memory. A first field of a save instruction encodes whether a value in a register of a processor is saved as an argument value or a static value. A second field of the save instruction encodes a size of a stack frame created during execution of the save instruction. An argument value is saved in a calling program's stack frame. A static value is saved in a called program's stack frame. A restore instruction is used to restore static values and deallocate the stack frame. The save and restore instructions may be executed using any programmable device, including a single instruction set architecture processor or a multi-instruction set architecture processor.

Abstract: A mechanism for processing in a processor enabled to support and execute multiple program threads includes a parameter for scheduling a program thread and an instruction disposed within the program thread and enabled to access the parameter. When the parameter equals a first value the instruction, when issued by a program thread, reschedules the program thread in accordance with one or more conditions encoded within the parameter.

Abstract: A mechanism for assuring quality of service for a context in a digital processor has a first scheduling register dedicated to the context, the register having N out of M bits set, and a first scheduler that consults the register to assign issue slots to the context. The first scheduler grants issue slots for the context by referencing the N bits in the first register, and repeats a pattern of assignments of issue slots after referencing the M bits of the first register.