Patents by Inventor Kevin M. Brandl

Kevin M. Brandl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220188024
    Abstract: A memory controller interfaces with a dynamic random access memory (DRAM). The memory controller selectively places memory commands in a memory interface queue and transmits the memory commands from the memory interface queue to a memory channel coupled to at least one dynamic random access memory (DRAM). An activate counter is maintained related to a number of activate commands sent over the memory channel to a memory region of the DRAM. In response to the activate counter being at or above a designated threshold, an arbiter is signaled that a refresh command should be sent to the memory region. In response to a designated condition, a value of the activate counter is adjusted by a total number based on a first fixed number and second varying number selected with one of random selection and pseudo-random selection.
    Type: Application
    Filed: December 10, 2020
    Publication date: June 16, 2022
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Kevin M. Brandl
  • Publication number: 20220122652
    Abstract: A memory controller interfaces with a random access memory over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the memory. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.
    Type: Application
    Filed: December 29, 2021
    Publication date: April 21, 2022
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Kedarnath Balakrishnan, Jing Wang, Guanhao Shen
  • Publication number: 20220091784
    Abstract: A memory controller includes a command queue having a first input for receiving memory access requests, and a memory interface queue having an output for coupling to a memory channel adapted for connecting to at least one dynamic random access memory (DRAM) module. A refresh control circuit monitors activate commands to be sent over the memory channel. In response to an activate command meeting a designated condition, the refresh control circuit identifies a candidate aggressor row associated with the activate command. A command is sent to the DRAM requesting that the candidate aggressor row be queued for mitigation in a future refresh or refresh management event.
    Type: Application
    Filed: September 21, 2020
    Publication date: March 24, 2022
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Kevin M. Brandl
  • Publication number: 20220076739
    Abstract: A system and method for use in dynamic random-access memory (DRAM) comprising entering into a self-refresh mode of operation, exiting the self-refresh mode of operation in response to commands from a self-refresh state machine memory operation (MOP) array, and updating a device state of the DRAM for a target power management state in response to commands from the MOP array.
    Type: Application
    Filed: November 15, 2021
    Publication date: March 10, 2022
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Naveen Davanam, Oswin E. Housty
  • Publication number: 20220028450
    Abstract: A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to the memory controller to initiate the stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request, periodically issuing a power platform threshold (PPT) request, by the SMU, to the memory controller, and sending a ForceZQCal command prior to a PPT request to ensure re-training occurs after ZQ Calibration. The ForceZQCal command issued prior to PPT request may reduce the latency of the stutter. The method may further include issuing a ForceZQCal command prior to each periodic re-training.
    Type: Application
    Filed: July 24, 2020
    Publication date: January 27, 2022
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Jing Wang, Kedarnath Balakrishnan, Kevin M. Brandl, James R. Magro
  • Patent number: 11221772
    Abstract: A system includes a memory system comprising a memory module and a processor adapted to access the memory module using a memory controller that includes a controller having an input for receiving a power state change request signal and an output for providing memory operations, and a memory operation array comprising a plurality of entries. Each entry includes a plurality of encoded fields. The memory operation array is programmable to store different sequences of commands for particular types of memory of a plurality of types of memory in the plurality of entries that initiate entry into and exit from supported low power modes for the particular types of memory. The controller is responsive to an activation of the power state change request signal to access the memory operation array to fetch at least one entry, and to issue at least one memory operation indicated by the at least one entry.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: January 11, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Thomas H. Hamilton
  • Patent number: 11222685
    Abstract: A memory controller interfaces with a dynamic random access memory (DRAM) over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the DRAM. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: January 11, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Kedarnath Balakrishnan, Jing Wang, Guanhao Shen
  • Publication number: 20210358540
    Abstract: A memory controller interfaces with a dynamic random access memory (DRAM) over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the DRAM. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 18, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Kedarnath Balakrishnan, Jing Wang, Guanhao Shen
  • Patent number: 11176986
    Abstract: Methods for reducing boot time of a system-on-a-chip (SOC) by reducing double data rate (DDR) memory training and memory context restore. Dynamic random access memory (DRAM) controller and DDR physical interface (PHY) settings are stored into a non-volatile memory and the DRAM controller and DDR PHY are powered down. On system resume, a basic input/output system restores the DRAM controller and DDR PHY settings from non-volatile memory, and finalizes the DRAM controller and DDR PHY settings for operation with the SOC. Reducing the boot time of the SOC by reducing DDR training includes setting DRAMs into self-refresh mode, and programing a self-refresh state machine memory operation (MOP) array to exit self-refresh mode and update any DRAM device state for the target power management state. The DRAM device is reset, and the self-refresh state machine MOP array reinitializes the DRAM device state for the target power management state.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: November 16, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Naveen Davanam, Oswin E. Housty
  • Publication number: 20210201986
    Abstract: Methods for reducing boot time of a system-on-a-chip (SOC) by reducing double data rate (DDR) memory training and memory context restore. Dynamic random access memory (DRAM) controller and DDR physical interface (PHY) settings are stored into a non-volatile memory and the DRAM controller and DDR PHY are powered down. On system resume, a basic input/output system restores the DRAM controller and DDR PHY settings from non-volatile memory, and finalizes the DRAM controller and DDR PHY settings for operation with the SOC. Reducing the boot time of the SOC by reducing DDR training includes setting DRAMs into self-refresh mode, and programing a self-refresh state machine memory operation (MOP) array to exit self-refresh mode and update any DRAM device state for the target power management state. The DRAM device is reset, and the self-refresh state machine MOP array reinitializes the DRAM device state for the target power management state.
    Type: Application
    Filed: December 30, 2019
    Publication date: July 1, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Naveen Davanam, Oswin E. Housty
  • Patent number: 10403333
    Abstract: A memory controller includes a host interface for receiving memory access requests including access addresses, a memory interface for providing memory accesses to a memory system, and an address decoder coupled to the host interface for programmably mapping the access addresses to selected ones of a plurality of regions. The address decoder is programmable to map the access addresses to a first region having a non-power-of-two size using a primary decoder and a secondary decoder each having power-of-two sizes, and providing a first region mapping signal in response. A command queue stores the memory access requests and region mapping signals. An arbiter picks the memory access requests from the command queue based on a plurality of criteria, which are evaluated based in part on the region mapping signals, and provides corresponding memory accesses to the memory interface in response.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: September 3, 2019
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Kevin M. Brandl, Thomas Hamilton, Hideki Kanayama, Kedarnath Balakrishnan, James R. Magro, Guanhao Shen, Mark Fowler
  • Publication number: 20190196720
    Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes one or more computing resources and a memory controller coupled to a memory device. The memory controller determines a memory access request targets a given bank of multiple banks. An access history is updated for the given bank based on whether the memory access request hits on an open page within the given bank and a page hit rate for the given bank is determined. The memory controller sets an idle cycle limit based on the page hit rate. The idle cycle limit is a maximum amount of time the given bank will be held open before closing the given bank while the bank is idle. The idle cycle limit is based at least in part on a page hit rate for the bank.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 27, 2019
    Inventors: Guanhao Shen, Ravindra N. Bhargava, James Raymond Magro, Kedarnath Balakrishnan, Kevin M. Brandl
  • Publication number: 20190196996
    Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory read requests have been sent to a memory device in a read mode of a data bus, the memory controller determines a threshold number of memory write requests to send to the memory device in an upcoming write mode is a number of outstanding memory write requests. Alternatively, the memory controller determines the threshold number of memory write requests to send to the memory device in an upcoming write mode is a maximum value of the number of outstanding memory write requests and a programmable value of the write burst length stored in a control register. Therefore, the write burst length is determined dynamically. Similarly, the read burst length is determined dynamically when the write mode ends.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 27, 2019
    Inventors: Kedarnath Balakrishnan, Ravindra N. Bhargava, Guanhao Shen, James Raymond Magro, Kevin M. Brandl
  • Publication number: 20190138234
    Abstract: A system includes a memory system comprising a memory module and a processor adapted to access the memory module using a memory controller that includes a controller having an input for receiving a power state change request signal and an output for providing memory operations, and a memory operation array comprising a plurality of entries. Each entry includes a plurality of encoded fields. The memory operation array is programmable to store different sequences of commands for particular types of memory of a plurality of types of memory in the plurality of entries that initiate entry into and exit from supported low power modes for the particular types of memory. The controller is responsive to an activation of the power state change request signal to access the memory operation array to fetch at least one entry, and to issue at least one memory operation indicated by the at least one entry.
    Type: Application
    Filed: January 7, 2019
    Publication date: May 9, 2019
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Thomas H. Hamilton
  • Patent number: 10198216
    Abstract: In one form, a data processing system includes a memory channel having a plurality of ranks, and a data processor. The data processor is coupled to the memory channel and is adapted to access each of the plurality of ranks. In response to detecting a predetermined event, the data processor selects an active rank of the plurality of ranks and places other ranks besides the active rank in a low power state, wherein the other ranks include at least one rank with a pending request at a time of detection of the predetermined event. The data processor subsequently processes a memory access request to the active rank.
    Type: Grant
    Filed: May 28, 2016
    Date of Patent: February 5, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kedarnath Balakrishnan, Kevin M. Brandl, James R. Magro
  • Patent number: 10198204
    Abstract: In one form, a memory controller includes a controller and a memory operation array. The controller has an input for receiving a power state change request signal and an output for providing memory operations. The memory operation array comprises a plurality of entries, each entry comprising a plurality of encoded fields. The controller is responsive to an activation of the power state change request signal to access the memory operation array to fetch at least one entry, and to issue at least one memory operation indicated by the entry. In another form, a system comprises a memory system and a processor coupled to the memory system. The processor is adapted to access the memory module using such a memory controller.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: February 5, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Thomas H. Hamilton
  • Patent number: 10067718
    Abstract: Dynamic random access memory (DRAM) chips in memory modules include multi-purpose registers (MPRs) having pre-defined data patterns which, when selected, are accessed with read commands and output on data lines for performing read training. The MPRs are accessed by issuing read commands to specific register addresses to request reads from specific MPR locations. In some embodiments, read training for memory modules includes addressing, for a first half of a memory module, a read command to a first register address and performing read training using a first set of bit values received in response to addressing using the first register address. For a second half of the memory module, the same read command is used, but read training is performed using a second set of bit values received in response to addressing using the first register address.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: September 4, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Glennis Eliagh Covington, Kevin M. Brandl, Nienchi Hu, Shannon T. Kesner
  • Patent number: 10042700
    Abstract: A post-package repair system includes a memory channel controller, a first error counter, a scrubber, and a data processor. The memory channel controller converts data access requests to corresponding memory accesses, and provides returned data to the host interface in response to responses received from a memory interface, wherein the responses comprise returned data and a plurality of error correcting code (ECC) bits. The first error counter counts errors in the returned data, and provides a control signal in response to reaching a predetermined state. The scrubber controls the memory channel controller to read data sequentially and periodically from a plurality of addresses of a memory system, and in response to detecting a correctable error, to rewrite corrected data. The data processor is responsive to the control signal to perform a post package repair operation with the memory system in response to the control signal.
    Type: Grant
    Filed: May 28, 2016
    Date of Patent: August 7, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Kevin M. Brandl
  • Patent number: 9965222
    Abstract: A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor includes a memory controller coupled to the memory channel and is adapted to access at least one rank of double data rate memory. The memory controller includes a command queue for storing received memory access requests, and an arbiter for picking memory access requests from the command queue, and then providing the memory access requests to the memory channel. The memory access requests are selected based on predetermined criteria, and in response to a mode register access request to quiesce pending operations. Additionally, the memory controller includes a mode register access controller that in response to the mode register access request, generates at least one corresponding mode register set command to a memory bus. The memory controller then relinquishes control of the memory bus to the arbiter thereafter.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: May 8, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Scott P. Murphy, James R. Magro, Paramjit K. Lubana
  • Publication number: 20180113648
    Abstract: A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor includes a memory controller coupled to the memory channel and is adapted to access at least one rank of double data rate memory. The memory controller includes a command queue for storing received memory access requests, and an arbiter for picking memory access requests from the command queue, and then providing the memory access requests to the memory channel. The memory access requests are selected based on predetermined criteria, and in response to a mode register access request to quiesce pending operations. Additionally, the memory controller includes a mode register access controller that in response to the mode register access request, generates at least one corresponding mode register set command to a memory bus. The memory controller then relinquishes control of the memory bus to the arbiter thereafter.
    Type: Application
    Filed: October 21, 2016
    Publication date: April 26, 2018
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Scott P. Murphy, James R. Magro, Paramjit K. Lubana