Patents by Inventor Kevin M. Brandl

Kevin M. Brandl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180088862
    Abstract: Dynamic random access memory (DRAM) chips in memory modules include multi-purpose registers (MPRs) having pre-defined data patterns which, when selected, are accessed with read commands and output on data lines for performing read training. The MPRs are accessed by issuing read commands to specific register addresses to request reads from specific MPR locations. In some embodiments, read training for memory modules includes addressing, for a first half of a memory module, a read command to a first register address and performing read training using a first set of bit values received in response to addressing using the first register address. For a second half of the memory module, the same read command is used, but read training is performed using a second set of bit values received in response to addressing using the first register address.
    Type: Application
    Filed: September 23, 2016
    Publication date: March 29, 2018
    Inventors: Glennis Eliagh Covington, Kevin M. Brandl, Nienchi Hu, Shannon T. Kesner
  • Publication number: 20180019006
    Abstract: A memory controller includes a host interface for receiving memory access requests including access addresses, a memory interface for providing memory accesses to a memory system, and an address decoder coupled to the host interface for programmably mapping the access addresses to selected ones of a plurality of regions. The address decoder is programmable to map the access addresses to a first region having a non-power-of-two size using a primary decoder and a secondary decoder each having power-of-two sizes, and providing a first region mapping signal in response. A command queue stores the memory access requests and region mapping signals. An arbiter picks the memory access requests from the command queue based on a plurality of criteria, which are evaluated based in part on the region mapping signals, and provides corresponding memory accesses to the memory interface in response.
    Type: Application
    Filed: July 15, 2016
    Publication date: January 18, 2018
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Thomas Hamilton, Hideki Kanayama, Kedarnath Balakrishnan, James R. Magro, Guanhao Shen, Mark Fowler
  • Publication number: 20170351450
    Abstract: In one form, a memory controller includes a controller and a memory operation array. The controller has an input for receiving a power state change request signal and an output for providing memory operations. The memory operation array comprises a plurality of entries, each entry comprising a plurality of encoded fields. The controller is responsive to an activation of the power state change request signal to access the memory operation array to fetch at least one entry, and to issue at least one memory operation indicated by the entry. In another form, a system comprises a memory system and a processor coupled to the memory system. The processor is adapted to access the memory module using such a memory controller.
    Type: Application
    Filed: June 1, 2016
    Publication date: December 7, 2017
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Thomas H. Hamilton
  • Publication number: 20170344421
    Abstract: A post-package repair system includes a memory channel controller, a first error counter, a scrubber, and a data processor. The memory channel controller converts data access requests to corresponding memory accesses, and provides returned data to the host interface in response to responses received from a memory interface, wherein the responses comprise returned data and a plurality of error correcting code (ECC) bits. The first error counter counts errors in the returned data, and provides a control signal in response to reaching a predetermined state. The scrubber controls the memory channel controller to read data sequentially and periodically from a plurality of addresses of a memory system, and in response to detecting a correctable error, to rewrite corrected data. The data processor is responsive to the control signal to perform a post package repair operation with the memory system in response to the control signal.
    Type: Application
    Filed: May 28, 2016
    Publication date: November 30, 2017
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Kevin M. Brandl
  • Publication number: 20170344309
    Abstract: In one form, a data processing system includes a memory channel having a plurality of ranks, and a data processor. The data processor is coupled to the memory channel and is adapted to access each of the plurality of ranks. In response to detecting a predetermined event, the data processor selects an active rank of the plurality of ranks and places other ranks besides the active rank in a low power state, wherein the other ranks include at least one rank with a pending request at a time of detection of the predetermined event. The data processor subsequently processes a memory access request to the active rank.
    Type: Application
    Filed: May 28, 2016
    Publication date: November 30, 2017
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Kedarnath Balakrishnan, Kevin M. Brandl, James R. Magro
  • Patent number: 9293188
    Abstract: In one form, a memory includes a memory bank, a page buffer, and an access circuit. The memory bank has a plurality of rows and a plurality of columns with volatile memory cells at intersections of the plurality of row and the plurality of columns. The page buffer is coupled to the plurality of columns and stores contents of a selected one of the plurality of rows. The access circuit is responsive to an adjacent command and a row address to perform a predetermined operation on the row address, and to refresh first and second addresses adjacent to the row address. In another form, a memory controller is adapted to interface with such a memory to select either a normal command or an adjacent command based on a number of activate commands sent to the row in a predetermined time window.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: March 22, 2016
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Kevin M. Brandl
  • Patent number: 9281046
    Abstract: A data processor includes a memory accessing agent and a memory controller. The memory accessing agent generates a plurality of accesses to a memory. The memory controller is coupled to the memory accessing agent and schedules the plurality of memory accesses in an order based on characteristics of the memory. The characteristics of the memory include a row cycle page time (tRCPAGE) indicative of an acceptable number of activate commands to a row in the memory within a predetermined time window.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: March 8, 2016
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Kevin M. Brandl
  • Patent number: 9214199
    Abstract: A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: December 15, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Oswin E. Housty, Gerald Talbot
  • Patent number: 9183125
    Abstract: A method is provided for sampling a data strobe signal of a memory cycle and determining a receiver enable phase based upon the data strobe signal. The method also includes performing a memory write cycle and a subsequent read cycle and training a read data strobe cycle at a one-quarter memory clock periodic offset. The method also includes determining a correct receiver enable delay in response to a successful read data strobe training cycle. Computer readable storage media are also provided. An apparatus is provided that includes a communication interface portion that is coupled to a memory portion and to a processing device. The apparatus also includes a first circuit portion, coupled to the communication interface portion. The first circuit portion monitors memory cycles on the communication interface portion, determines a receiver enable cycle phase and train a receiver enable cycle without using receiver enable seed.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: November 10, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Oswin E. Housty, Edoardo Prete, Gerald Talbot
  • Patent number: 9141541
    Abstract: A system and method for mapping an address space to a non-power-of-two number of memory channels. Addresses are translated and interleaved to the memory channels such that each memory channel has an equal amount of mapped address space. The address space is partitioned into two regions, and a first translation function is used for memory requests targeting the first region and a second translation function is used for memory requests targeting the second region. The first translation function is based on a first set of address bits and the second translation function is based on a second set of address bits.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: September 22, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vydhyanathan Kalyanasundharam, Kevin M. Brandl, Adnan Dhanani
  • Publication number: 20150221358
    Abstract: In one form, a memory includes a memory bank, a page buffer, and an access circuit. The memory bank has a plurality of rows and a plurality of columns with volatile memory cells at intersections of the plurality of row and the plurality of columns. The page buffer is coupled to the plurality of columns and stores contents of a selected one of the plurality of rows. The access circuit is responsive to an adjacent command and a row address to perform a predetermined operation on the row address, and to refresh first and second addresses adjacent to the row address. In another form, a memory controller is adapted to interface with such a memory to select either a normal command or an adjacent command based on a number of activate commands sent to the row in a predetermined time window.
    Type: Application
    Filed: February 3, 2014
    Publication date: August 6, 2015
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventor: Kevin M. Brandl
  • Publication number: 20150100723
    Abstract: A data processor includes a memory accessing agent and a memory controller. The memory accessing agent generates a plurality of accesses to a memory. The memory controller is coupled to the memory accessing agent and schedules the plurality of memory accesses in an order based on characteristics of the memory. The characteristics of the memory include a row cycle page time (tRCPAGE) indicative of an acceptable number of activate commands to a row in the memory within a predetermined time window.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 9, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Kevin M. Brandl
  • Publication number: 20150089168
    Abstract: A system and method for mapping an address space to a non-power-of-two number of memory channels. Addresses are translated and interleaved to the memory channels such that each memory channel has an equal amount of mapped address space. The address space is partitioned into two regions, and a first translation function is used for memory requests targeting the first region and a second translation function is used for memory requests targeting the second region. The first translation function is based on a first set of address bits and the second translation function is based on a second set of address bits.
    Type: Application
    Filed: September 20, 2013
    Publication date: March 26, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Vydhyanathan Kalyanasundharam, Kevin M. Brandl, Adnan Dhanani
  • Publication number: 20150078104
    Abstract: A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.
    Type: Application
    Filed: September 26, 2014
    Publication date: March 19, 2015
    Inventors: Kevin M. Brandl, Oswin E. Housty, Gerald Talbot
  • Patent number: 8850155
    Abstract: A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: September 30, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Oswin E. Housty, Gerald Talbot
  • Publication number: 20130155788
    Abstract: A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.
    Type: Application
    Filed: December 19, 2011
    Publication date: June 20, 2013
    Inventors: Kevin M. Brandl, Oswin E. Housty, Gerald Talbot
  • Publication number: 20130159615
    Abstract: A method is provided for sampling a data strobe signal of a memory cycle and determining a receiver enable phase based upon the data strobe signal. The method also includes performing a memory write cycle and a subsequent read cycle and training a read data strobe cycle at a one-quarter memory clock periodic offset. The method also includes determining a correct receiver enable delay in response to a successful read data strobe training cycle. Computer readable storage media are also provided. An apparatus is provided that includes a communication interface portion that is coupled to a memory portion and to a processing device. The apparatus also includes a first circuit portion, coupled to the communication interface portion. The first circuit portion monitors memory cycles on the communication interface portion, determines a receiver enable cycle phase and train a receiver enable cycle without using receiver enable seed.
    Type: Application
    Filed: December 19, 2011
    Publication date: June 20, 2013
    Inventors: Kevin M. Brandl, Oswin E. Housty, Edoardo Prete, Gerald Talbot