Abstract: An integrated circuit comprising a receiver, a transmitter, and a frequency lock loop configured to supply clock signals to the receiver and transmitter, the frequency lock loop including a current source having a thermal voltage generator, a current controlled oscillator having a plurality of selectively engageable current mirrors multiplying up the current of the current source, the frequency of the frequency lock loop varying in response to selection of the current mirrors, the current mirrors including transistors operating in a subthreshold mode.

Abstract: A radio frequency identification device comprises an integrated circuit including a receiver, a transmitter, and a microprocessor. The receiver and transmitter together define an active transponder. The integrated circuit is preferably a monolithic single die integrated circuit including the receiver, the transmitter, and the microprocessor. Because the device includes an active transponder, instead of a transponder which relies on magnetic coupling for power, the device has a much greater range.

Abstract: A semiconductor wafer has multiple individual dies containing integrated circuits arrayed for singulation and test cycling circuitry for test cycling individual dies. A passivation layer overlies the dies, with contact openings being provided through the passivation layer to Vcc and Vss pads. The semiconductor wafer also has Vcc and Vss buses provided atop the passivation layer and overlying the individual dies to connect with the underlying Vcc and Vss pads, respectively. In this manner, application of voltage to the Vcc and Vss buses provides simultaneous test cycling of all the underlying dies on the semiconductor wafer. A semiconductor wafer processing fixture for conducting the burn-in test cycling of such a semiconductor wafer is also disclosed. The fixture has a wafer cavity sized to receive and register the semiconductor wafer in a selected orientation and an electrical connector having pins designed to contact the overlying busing structure on the semiconductor wafer.

Abstract: A semiconductor wafer comprises a plurality of individual dies containing integrated circuits which are substantially isolated from each other. The wafer is severable between the dies to physically singulate the dies from each other. The wafer includes test cycling circuitry for test cycling the individual dies. A Vcc bus and a Vss bus overly a passivation layer and are electrically connected through the passivation layer with Vcc and Vss pads associated with the individual dies.

Abstract: A method of processing and testing a semiconductor wafer containing an array of integrated circuit dies comprises: a) providing die test cycling circuitry on the wafer b) etching contact openings through a passivation layer atop the wafer to Vcc and Vss pads associated with individual dies; c) patterning a layer of conductive material atop the water to provide a Vcc bus and a Vss bus which interconnect with the Vcc and Vss pads respectively, the Vcc bus electrically connecting with the test cycling circuitry; d) burn-in testing the wafer with selected voltages being applied to the Vss and Vcc buses e) etching the Vcc bus and Vss bus from the wafer; f) etching contact openings through the passivation layer to conductive pads on individual dies; g) testing the individual dies for operability by engaging the conductive pads with testing equipment; h) identifying operable dies; i) singulating the dies; and j) collecting the operable dies.