Abstract: Systems and methods are disclosed to mitigate power consumption in a power supply, such as when operating in a low power mode. One aspect of the present invention relates to a control system for a power supply. The system includes a bias generator that provides a bias signal operative to charge a storage device based on a control signal. During a low power mode, a control system provides the control signal with a predetermined duty cycle that is functionally related to a storage capacity of the storage device.

Abstract: A modified flow for ASIC place an route software flow which allows incorporation into the flow, a process for tracking the locations of substrate contacts and well-ties within and outside the boundaries of placed cells and generating required supplemental placements, making possible an efficient use of silicon chip area expended in the adequate placement of substrate contacts and well-ties.

Abstract: An integrated circuit (IC) comprising an integrated level shifting latch for I/O. The level shift in the IC I/O section may be clocked. In addition, a latch may be moved from the core section to the I/O section of the device, and thus the incoming clock may remain in the external voltage domain to clock the latch along with the level shift. The level shift and latch may be clocked on opposite phases of the clock. Preferably, the level shift and latch may operate differentially on the data signal. Both setup and clock-to-Q times are significantly reduced with respect to prior art devices, allowing higher speed industry specifications may be met.

Abstract: An integrated circuit (IC) comprising an integrated level shifting latch for I/O. The level shift in the IC I/O section may be clocked. In addition, a latch may be moved from the core section to the I/O section of the device, and thus the incoming clock may remain in the external voltage domain to clock the latch along with the level shift. The level shift and latch may be clocked on opposite phases of the clock. Preferably, the level shift and latch may operate differentially on the data signal. Both setup and clock-to-Q times are significantly reduced with respect to prior art devices, allowing higher speed industry specifications may be met.

Abstract: A phase/frequency detector (18) includes a first memory circuit (50), a second memory circuit (52), a first set circuit (54), a second set circuit (58) and a reset circuit (56). The first memory circuit (50) provides a first output signal (20) in response to the first input signal (12). The second memory circuit (52) provides a second output signal (22) in response to the second input signal (14). The first set circuit (54) initiates the transition of the first memory circuit (50) to the active state, and the second set circuit (58) initiates the transition of the second memory circuit (52) to the active state. The reset circuit (56) initiates the transition of the memory circuits (50, 52) to the inactive state.

Abstract: An integrated circuit (100) contains an analog phase-locked loop circuit having a phase detector circuit (16) which compares the phase of a reference signal (28) to the output (12) of the phase-locked loop circuit, a charge pump circuit (18) responsive to the phase detector circuit for varying the charge on a capacitor (36) of a loop filter circuit (20), a regulator circuit (22) which receives two separate control voltages (38, 44) from the loop filter circuit, and a voltage controlled oscillator circuit (24) which receives from the regulator circuit two separate control voltages (VIN, VREG). The voltage controlled oscillator circuit is designed to work with a relatively low regulated voltage, and the regulator circuit is implemented with n-channel devices. The two control voltages respectively effect coarse and fine adjustment of the frequency of the output signal from the phase-locked loop circuit.

Abstract: An integrated circuit (100) includes an analog phase-locked loop circuit (10) and other circuitry (102). The integrated circuit (100) has a plurality of external connection pins (104, 106), which are coupled to the other circuitry. The analog phase-locked loop circuit (10) is free of connections to the external connection pins. The analog phase-locked loop circuit (10) includes a phase detector circuit (16) which compares the phase of a reference signal (28) to the output (12) of the phase-locked loop circuit, a charge pump circuit (18) responsive to the phase detector for varying the charge on a capacitor (36) of a loop filter circuit (20), a regulator circuit (22) which receives two separate control voltages (38, 44) from the loop filter circuit, and a voltage controlled oscillator circuit (24) which receives from the regulator circuit two separate control voltages (VIN, VREG) and a regulated supply voltage (VREG).

Abstract: An integrated circuit (100) includes an analog phase-locked loop circuit (10) and other circuitry (102). The analog phase-locked loop circuit includes a phase detector circuit (16) which compares the phase of a reference signal (28) to the output (12) of the phase-locked loop circuit, a charge pump circuit (18) responsive to the phase detector for varying the charge on a capacitor (36) of a loop filter circuit (20), a regulator circuit (22) which receives two separate control voltages (38, 44) from the loop filter circuit, and a voltage controlled oscillator circuit (24) which receives from the regulator circuit two separate control voltages (VIN, VREG), one of which also serves as a regulated supply voltage. The regulator circuit includes n-channel devices which are connected in series between a supply voltage and each control voltage output.

Abstract: A lock detector (16) includes a set circuit (64), a reset circuit (120), and a latch circuit (80). The latch circuit (80) provides an output signal (82) in response to the temporal relationship of the first input signal (12) and the second input signal (14). The set circuit (64) initiates the transition of the latch circuit (80) to the locked state, while the reset circuit (120) initiates the transition of the latch circuit (80) to the not-locked state.

Abstract: A digital data signal voltage converter for converting a first digital data signal that is asserted at a first pair of voltage levels that are considered the inverse of one another, the two voltage levels being a first low voltage level and a first high voltage level, to a second digital data signal that is asserted at a second pair of voltage levels that are considered the inverse of one another, the second pair of voltage levels being a second low voltage level and a second high voltage level, the second high voltage level being higher than the first high voltage level. The voltage converter includes an active pull-up transistor and an active pull-down transistor, along with circuitry for controlling the second high voltage level. Three-state control may be provided to allow use as an input/output terminal.

Abstract: An integrated circuit (42) is formed in a semiconductor layer (50) having a defined area. Functional circuitry (12) is formed in semiconductor layer (50) to occupy only a portion of the defined area of semiconductor layer (50), and thus defining an unoccupied area of semiconductor layer (50). A capacitor is formed in semiconductor layer in a substantial portion of the unoccupied area.

Abstract: A process variance detection technique for detecting fabrication processing variances in integrated circuit components, such as resistors or MOSFETs, is based on the decreased sensitivity to processing variations exhibited by components that are up-sized relative to similar components with nominal dimensions. Detection circuitry includes detection components with both nominal and up-sized dimensions, and variance detection involves detecting the differences in operational response of the nominal and up-sized detection components. For bipolar logic, resistors are fabricated with up-sized widths, while for MOS logic, MOSFETs are fabricated with up-sized gate lengths.

Abstract: A flip-flop having a master section including two switching transistors is provided with output loading transistors to drive the two transistors into saturation in the event of a metastable condition causing input is present. By driving the switching transistors into saturation they become inactive and background noise cannot cause proprogation of the metastable condition to subsequent flip-flip stages.

Abstract: A TTL gate (26) with a Darlington output (14,14A,16) includes three circuits (28,30,32) to decrease the gate switching time during an output transition from a high to a low logic state and from a high impedance state to a low logic state. Each speedup circuit drives the gate input transistor (12) for a different length of time, ensuring that the lower output transistor (16) turns on rapidly and remains on until the output transition is complete. The circuits ensure, however, that the additional drive current (82) is time limited to avoid excessive power consumption.

Abstract: In one aspect of the present invention, a converter is provided comprising a capacitive coupling arranged to receive said input signal to be converter, and a conversion circuitry coupled to the capacitive coupling to produce the converted output signal. A biasing circuit is further arranged to facilitate a fast transition in the converted output signal in response to an active transition in the input signal.

Abstract: A test circuit (10) is connected to a package pin of an integrated circuit via the first node (16). By setting the voltage on the package pin to a sufficient voltage, the test circuit becomes operable to measure DC characteristics of devices in the test circuit. The DC characteristics of the test circuit devices, such as resistors (26 and 34), diodes (44) and transistors (30 and 32) are used to estimate the AC characteristics of the actual integrated circuit. The AC characteristic estimations may be used to screen parts into various speed classes.

Abstract: An ECL gate (32) includes a speedup circuit (34) comprising an NPN transistor (36) having its base connected to the IN signal to the gate (32). The PNP transistor drives an NPN transistor (40) to provide faster output transitions responsive to low-to-high transition to the IN signal.

Abstract: An improved buffer circuit with a low-pass filter includes a first variable resistance which forms the input of the buffer circuit and is connected to a clamp circuit, a variable capacitor, a second variable resistance, a third variable resistance, and a buffer. A first compensation circuit is connected between the buffer and the second variable resistance. A second compensation circuit is connected between the buffer and the third variable resistance. First and second compensation circuits provide feedback paths through the second and third variable resistances which enable the voltage at the node connecting the first variable resistance, the clamp circuit, the variable capacitor, and the buffer to be "pulled up" or "pulled down" depending upon the signal transition at the input thereby following the node voltage a the buffer circuit input more quickly thus reducing recovery time and allowing the buffer circuit to concurrently filter noise and increase switching frequency.

Abstract: A method and circuitry are provided for latching a logic state. A first signal (64) indicates a logic state of an input signal (D) in response to a first transition of a clock signal (72). A second signal (68) indicates a logic state of the first signal (64) in response to a second transition of the clock signal (72). An output signal (Q) indicates the logic state of the first signal (64) in response to the second transition and indicates a logic state of the second signal (68) in response to the first transition.

Abstract: A test circuit (10) is connected to a package pin of an integrated circuit via the first node (16). By setting the voltage on the package pin to a sufficient voltage, the test circuit becomes operable to measure DC characteristics of devices in the test circuit. The DC characteristics of the test circuit devices, such as resistors (26 and 34), diodes (44) and transistors (30 and 32) are used to estimate the AC characteristics of the actual integrated circuit. The AC characteristic estimations may be used to screen parts into various speed classes.