Abstract: An integrated circuit (42) is formed in a semiconductor layer (50) having a defined area. Functional circuitry (12) is formed in semiconductor layer (50) to occupy only a portion of the defined area of semiconductor layer (50), and thus defining an unoccupied area of semiconductor layer (50). A capacitor is formed in semiconductor layer in a substantial portion of the unoccupied area.

Abstract: A synchronized pulsed look-ahead circuit (10 in FIG. 1) effects look-ahead operations for a flip-flop (20). It includes a LAPP section (12) and a DATA sense and control section (14). To initiate a look-ahead operation, the LAPP section triggers in synchronism with the control edge of CLK, swtiching the LAPP line active and enabling the DATA sense and control section. While enabled, the DATA sense and control section receives DATA IN, and depending on its phase, provides the appropriate logic levels to the DATA output driver, which then provides the appropriate DATA OUT. When the flip-flop has latched the DATA and is ready to assume control of the DATA OUT line, i.e., after the associated propagation delay, the LAPP pulse is terminated and the DATA sense and control section is disabled, terminating the look-ahead operation.

Abstract: A hybrid CMOS-bipolar memory cell for a high speed memory includes a CMOS latch which has two storage nodes (104) and (106) for storing two logic states. The CMOS latch is disposed between a high voltage node (110) and a low voltage node (114). The two nodes are maintained at a predetermined voltage to maintain a static state. A bipolar current drive transistor (120) is provided which is connected to one of the storage nodes (106) to provide a low source impedance for output from the memory cell. A work line (44) is connected to the high voltage node (110) for selection thereof by varying between two predetermined voltages. The cell is written to be selectively discharging either node (104) or (106) to a low voltage node (114) through bipolar transistors (122) and (124). The bipolar transistor (122) and (124) provide high transconductance switches for selectively discharging the storage nodes (104) and (106).

Abstract: A memory device (10) includes switching circuitry 22 comprising sensing and control circuits (24 and 26) to predict the next state of the output of memory device (12) and to turn on and off current sources (20) responsive to said memory output to provide faster output transitions.

Abstract: A multiplying circuit (10) receives a multiplicand A and multiplies it by multiplier B. An Octal recoder (18) recodes the multiplier B into octal digits having a value from 4 to -4. A tripling generator determines the product of three times the multipicand. Partial product generators (22a-h) connected to the Octal recoder multiplex between the multiplicand A and the 3*A product, and include shifter and inverter circuitry to generate the partial products. Signed digit adders (24a-d, 26a-b and 28) add the partial products.

Abstract: An active pull down circuit for a logic circuit, having a true and a complement output, a pull down transistor coupled to one of the true and complement outputs, a bias element for biasing the pull down transistor on, and a charge coupling element coupled between the other of the true and complement outputs and a base of the pull down transistor for coupling charge from the other output to the pull down transistor to turn on the latter harder when the other output goes low.

Abstract: A TTL gate (22) includes a current generating circuit (24) comprising an NPN transistor (30) having its base coupled to a diode (24) and its emitter coupled to one of the gate's output transistors (14). Transistor (30) enables diode (24) to deliver a high current of short duration to the output OUT responsive to a low-to-high output transition. The current provides low-to-high output transition while protecting output transistor (14) from damaging currents caused by a short circuit at output OUT.

Abstract: Conversion from a first set of logic levels, such as ECL levels, to a second set of logic levels, such as TTL, is performed by using a regulator (46) and is parallel to the circuit generating the first set of logic levels.

Abstract: A sense amplifier 10 for a memory or logic array has a bipolar device transistor 11 that is kept from saturating by one or more unipolar transistors (12, 13) coupled between the collector (18) and base (17) of the bipolar transistor 11.

Abstract: The disclosure relates to a method of making a logic circuit wherein the voltage regulators of the ECL circuits, which use resistor ratios, the values of which are difficult to control in the formation of semiconductor circuits, are replaced by a series of diodes, the areas of which are very easy to control in semiconductor fabrication, to set the threshold voltages for the transistors. Embodiments are disclosed using the basic circuit in a stacked configuration to provide AND/NAND operation in addition to the OR/NOR operation of the basic embodiment.

Abstract: The disclosure relates to an STL flip flop circuit composed of a pair of latch circuits, the first latch circuit receiving R and S inputs and the clock signal and floating relative to the other latch circuit. The second latch circuit is referenced to ground and is driven by the output of the floating latch circuit. All components are of the schottky type, the semiconductor devices being schottky clamp transistors and the diodes being either TiW or PtSi type. In accordance with a second embodiment of the invention, a pair of inverter circuits are each coupled to the R and S inputs of the first embodiment, one of the inverters being controlled by an external data source, whereby, the inverters always each provide opposite outputs to the R and S inputs, depending upon the data input. Schottky clamp transistors and two different types of schottky diodes are utilized.

Abstract: A logic circuit which includes first and second differentially connected amplifying devices having first and second complementary output voltage nodes. Means for limiting the output voltage swing of the devices at the output nodes to a predetermined range reduces the required voltage supply source. A reference voltage is coupled to the second amplifying device while a plurality of input diodes are coupled in parallel to an input of the first amplifying device to form AND inputs thereto. A biasing element is coupled to the input of the first amplifying device.

Abstract: A flip-flop has a master section (74) comprising two transistors (40, 48). The second transistor (48) has two emitters, the second emitter conducting in response to a metastable condition wherein both transistors (40,48) are conducting concurrently, resulting in a metastable output. The second emitter (76) draws additional current through the second transistor (48) after a delay provided by a second clock (78), thus disrupting the equilibrium of the master section (74). By drawing additional current, the second transistor (48) will turn the first transistor (40) off, enabling a valid output.

Abstract: The disclosure relates to a logic circuit wherein the voltage regulators of the ECL circuits, which use resistor ratios, the values of which are difficult to control in the formation of semiconductor circuits, are replaced by a series of diodes, the areas of which are very easy to control in semiconductor fabrication, to set the threshold voltages for the transistors. Diode voltage ratios are very controllable since the diodes change only about 18 millivolts for every factor of two in current change. Thresholds can therefore easily be set in five and ten millivolt increments, this being the procedure utilized herein. Embodiments are disclosed using the basic circuit in a stacked configuration to provide AND/NAND operation in addition to the OR/NOR operation of the basic embodiment.

Abstract: A voltage reference circuit which includes a first diode having a first predetermined forward voltage drop as a function of current, a second diode having a second predetermined forward voltage drop as a function of current, lower by a preselected amount than said first diode voltage drop and connected to a voltage reference node and to one end of said first diode. A resistor is connected to the voltage reference node and to another end of the first diode such that the second diode and the resistor form a current path around the first diode. The arrangement is such that the temperature coefficient of voltage at the voltage reference node is less than that across the first diode.

Abstract: The disclosure relates to a shottky transistor logic (STL) exclusive-OR circuit with a buffer wherein the gate portion uses a pair of shottky clamp transistors having the base electrode of each cross coupled to the emitter of the other transistor through a schottky diode. Provision is made to provide and AND function at the input by providing plural emitters, each coupled to a separate input, on one of the transistors. A buffer circuit is provided to assit in operation at two volts rather than five volts.

Abstract: A read-back latch circuit which includes a latch circuit having an input and an output and an enable input and operative to transmit an input data signal to the output in response to a preselected enable signal and to block the transmission of the input data signal otherwise. A read-back switch is coupled between the output and input of said latch circuit and is operative to couple the signal on the output of said latch circuit to the input thereof in response to a read-back control signal.

Abstract: The disclosure relates to an STL bipolar buffer/driver circuit having a low output impedance for driving capacitive leads and the like wherein the output resistor of the prior art circuits is replaced by an NPN bipolar transistor and a further circuit including a series resistor, schottky diode and schottky clamp transistor for controlling the two output transistors.

Abstract: The specification discloses a transition speed up circuit including an input transistor (14) for receiving a variable input voltage. An output transistor (16) is connected to the input transistor (14) to receive turn on current. A first diode (32) is connected at its cathode to the collector of the input transistor (14). A resistor (46) is connected between the anode of diode (32) and the output terminal (18). A speed up transistor (42) is connected at its emitter to the collector of input transistor (14) to supply speed up current through input transistor (14) to output transistor (16). A second diode (44) is connected between the base of speed up transistor (42) and the junction of first diode (32) and resistor (46). The speed up current terminates when the voltage at the output terminal (18) falls to a level determined by the value of resistor (46).

Abstract: The specification discloses an input transistor (14) which is variable between high and low impedance states in response to input voltage transitions at terminal 10. An output transistor (16) is coupled to the input transistor (14) and is responsive to an input transition at terminal 10 for changing impedance states. Circuitry including a speed up transistor (44) is coupled between the input transistor (14) and output transistor (16) for applying added current to the output transistor (16) to speed the change of impedance state. The circuitry applies added current to output transistor (16) until the output voltage at terminal (18) falls below twice the base-emitter voltage of the output transistor (16).