Abstract: Various embodiments relate to a bias generator including: a bias generator circuit; a master startup circuit that applies current to a first node in the bias generator circuit; a second startup circuit that applies current to additional nodes in the bias generator circuit; and a power switch that receives a power from a power supply and that provides power to the bias generator circuit, the master startup circuit, and the second startup circuit.

Abstract: Power supply is facilitated. In accordance with one or more embodiments, a power regulator circuit includes first and second regulators and a controller for controlling operation of the power regulator circuit in standby and normal operational modes. The first and second regulators respectively provide regulated power at main and standby power levels, the standby power level being lower than the main power level. For the standby mode, the controller operates the second regulator for supplying power to an integrated circuit at the standby power level. For transitioning to the normal mode, the controller turns the first regulator on while continuing to operate the second regulator for supplying power to the integrated circuit during a start-up period. After a start-up period (e.g., when the first regulator is up to full power), the controller operates the first regulator for supplying power for operating the processor in a high-frequency mode.

Abstract: Methods, devices and circuits are provided for power-on-reset circuits with low static power consumption. One such circuit includes a detector that draws current from a supply voltage. The detector detects that the supply voltage has exceeded a trip-point voltage level and then disables current draw from the detector. The detector responds to an enable signal by enabling current draw from the detector. A pulse generator generates a reset signal in response the supply voltage transitioning from a voltage below the trip point voltage level to above the trip point voltage level. A monitor detects that the supply voltage has dropped and provides, in response thereto, the enable signal to the detector to enable current draw from the portion of the detector.

Abstract: A Complementary Metal Oxide Semiconductor (CMOS) power switching circuit and a method for operating a CMOS power switching circuit are described. In one embodiment, a CMOS power switching circuit includes a voltage selection circuit configured to output the highest output voltage between an output voltage of a primary power supply and an output voltage of a backup power supply and a control circuit configured to connect a load circuit to either the primary power supply or the backup power supply by comparing the output voltage of the primary power supply with a power supply switchover level that is set as a function of the highest output voltage. The backup power supply serves as a voltage reference to set the power supply switchover level only when the output voltage of the primary power supply is lower than the output voltage of the backup power supply. Other embodiments are also described.

Abstract: A system for power regulation is provided. The system includes a plurality of regulator stages and a voltage boost circuit configured to provide a source voltage to a difference amplifier of each regulator stage. The difference amplifier of each regulator stage is configured to compare a feedback voltage to an output voltage of a reference generation circuit. Each regulator stage includes a plurality of output transistors driven by an output of the difference amplifier. The system includes a start-up circuit arranged and configured to power the voltage boost circuit the reference generation circuit while operation in a start up mode.

Abstract: Consistent with an example embodiment, there is a power regulator arrangement with variable current capacity providing power from a power supply to a load having variable demand. As a load, a high-performance microprocessor has several modes of operation. At the highest speed setting, it demands a lot of current. At slower clock speeds and during state retention, the processor has a very low current consumption. Using a single regulator, the current efficiency may be very low during long standby periods. To increase the efficiency even at lower load currents, a scheme is based on parallel operation of multiple regulators having different load ranges, for example, a “low, “medium,” and “high” range regulators. Having knowledge of the load current profile, the regulators can be adjusted such that the peak of the efficiency curve matches the load profile of the regulator. The efficiency of the power regulator arrangement is enhanced throughout the range of power demanded by the load.

Abstract: A method for generating a reference voltage includes generating a proportional-to-absolute temperature (PTAT) voltage across a first pseudo resistor. The first pseudo resistor includes a transistor. The method also includes converting the PTAT voltage to a current based on a resistance of the first pseudo resistor. The method also includes mirroring the current using a current mirror circuit and converting the mirrored current to a converted PTAT voltage using a second pseudo resistor. The second pseudo resistor includes a transistor. The first pseudo resistor and the second pseudo resistor include equal transistor types. The method also includes generating a complementary-to-absolute temperature (CTAT) voltage, and summing the converted PTAT voltage and the CTAT voltage to produce the reference voltage. The resulting reference voltage is temperature independent.

Abstract: A reference circuit, an oscillator architecture that includes the reference circuit and a method for operating the reference circuit are described. In one embodiment, the reference circuit includes a voltage reference generator configured to generate a reference voltage and a current reference generator configured to generate a reference current based on the reference voltage. The current reference generator includes a level shifter circuit configured to generate intermediate voltages based on the reference voltage, a first current reference circuit configured to generate intermediate currents based on the intermediate voltages, where the intermediate currents are correlated to the reference voltage, and a second current reference circuit configured to combine the intermediate currents to generate the reference current. Other embodiments are also described.

Abstract: A method for generating a reference voltage is disclosed. The method includes generating a proportional-to-absolute temperature (PTAT) voltage across a first pseudo resistor. The first pseudo resistor includes a transistor. The method also includes converting the PTAT voltage to a current based on a resistance of the first pseudo resistor. The method also includes mirroring the current using a current mirror circuit and converting the mirrored current to the PTAT voltage using a second pseudo resistor. The second pseudo resistor includes a transistor. The first pseudo resistor and the second pseudo resistor include equal transistor types. The method also includes generating a complimentary-to-absolute temperature (CTAT) voltage, and summing the converted PTAT voltage and the CTAT voltage to produce the reference voltage. The resulting reference voltage is temperature independent.

Abstract: A reference circuit, an oscillator architecture that includes the reference circuit and a method for operating the reference circuit are described. In one embodiment, the reference circuit includes a voltage reference generator configured to generate a reference voltage and a current reference generator configured to generate a reference current based on the reference voltage. The current reference generator includes a level shifter circuit configured to generate intermediate voltages based on the reference voltage, a first current reference circuit configured to generate intermediate currents based on the intermediate voltages, where the intermediate currents are correlated to the reference voltage, and a second current reference circuit configured to combine the intermediate currents to generate the reference current. Other embodiments are also described.

Abstract: A method and apparatus for correcting the offset and linearity error of a data acquisition system. A charge redistribution digital to analog convertor (CDAC) is connected to one of the differential inputs of a comparator whose second input comes from a function CDAC. The calibration algorithm is built into a digital control unit. The digital control unit detects the offset and capacitor mismatch errors sequentially, stores the calibration codes for each error in calibration mode and provides the input-dependent error correction signals synchronized with the binary search timing to adjust the differential input of the comparator and compensate the input-dependent errors present at the output of the non-ideal function CDAC during normal conversions.

Abstract: Power control is facilitated. In accordance with one or more embodiments, power is supplied to power rails of an integrated circuit using a power control circuit including a power regulator and a reset circuit that is responsive to a supply voltage. The power regulator provides power to the power rails, based upon a control signal. The reset circuit controls the power regulator to provide power to the power rails independently of the control signal when the supply voltage is below an operational voltage level, and controls the power regulator to provide power to the power rails in response to the control signal when the supply voltage reaches the operational voltage level.

Abstract: An apparatus implements analog-to-digital conversion with released requirement on the reference settling errors and improved immunity to the noise originated from the power supply, ground and the positive and negative references. It includes a comparator comparing the specified reference levels with the analog input, multi DAC sub-circuits with separate non-binary search schemes applied to and a digital control logic controlling the reference search process. No cross-talk occurs among the different non-binary search algorithms. Each redundancy scheme is localized in a respective DAC sub-circuit and covers the reference levels only in the current DAC. The non-binary search algorithms are fulfilled in the digital domain and trade the non-binary search step sizes with the number of the search steps to introduce redundancy to the reference levels.

Abstract: A Complementary Metal Oxide Semiconductor (CMOS) power switching circuit and a method for operating a CMOS power switching circuit are described. In one embodiment, a CMOS power switching circuit includes a voltage selection circuit configured to output the highest output voltage between an output voltage of a primary power supply and an output voltage of a backup power supply and a control circuit configured to connect a load circuit to either the primary power supply or the backup power supply by comparing the output voltage of the primary power supply with a power supply switchover level that is set as a function of the highest output voltage. The backup power supply serves as a voltage reference to set the power supply switchover level only when the output voltage of the primary power supply is lower than the output voltage of the backup power supply. Other embodiments are also described.

Abstract: An apparatus implements analog-to-digital conversion with released requirement on the reference settling errors and improved immunity to the noise originated from the power supply, ground and the positive and negative references. It includes a comparator comparing the specified reference levels with the analog input, multi DAC sub-circuits with separate non-binary search schemes applied to and a digital control logic controlling the reference search process. No cross-talk occurs among the different non-binary search algorithms. Each redundancy scheme is localized in a respective DAC sub-circuit and covers the reference levels only in the current DAC. The non-binary search algorithms are fulfilled in the digital domain and trade the non-binary search step sizes with the number of the search steps to introduce redundancy to the reference levels.

Abstract: In one embodiment, a regulator circuit is provided. The regulator circuit includes a control circuit configured and arranged to adjust an oscillation frequency of a variable frequency oscillator in response to a feedback signal indicating the regulated output voltage. A charge pump is coupled to an output of the variable frequency oscillator and is configured to charge one or more energy storage elements in response to the output of the variable frequency oscillator. The regulator circuit includes a plurality of output stages, each having an input driven by the output of the charge pump and being configured to drive the regulated output voltage. Each output stage is selectably enabled or disabled in response to respective enable signal provided to the output regulator by an enable control circuit.

Abstract: A method and apparatus for correcting the offset and linearity error of a data acquisition system. A charge redistribution digital to analog convertor (CDAC) is connected to one of the differential inputs of a comparator whose second input comes from a function CDAC. The calibration algorithm is built into a digital control unit. The digital control unit detects the offset and capacitor mismatch errors sequentially, stores the calibration codes for each error in calibration mode and provides the input-dependent error correction signals synchronized with the binary search timing to adjust the differential input of the comparator and compensate the input-dependent errors present at the output of the non-ideal function CDAC during normal conversions.

Abstract: A system for power regulation is provided. The system includes a plurality of regulator stages and a voltage boost circuit configured to provide a source voltage to a difference amplifier of each regulator stage. The difference amplifier of each regulator stage is configured to compare a feedback voltage to an output voltage of a reference generation circuit. Each regulator stage includes a plurality of output transistors driven by an output of the difference amplifier. The system includes a start-up circuit arranged and configured to power the voltage boost circuit the reference generation circuit while operation in a start up mode.

Abstract: Various embodiments relate to a bias generator including: a bias generator circuit; a master startup circuit that applies current to a first node in the bias generator circuit; a second startup circuit that applies current to additional nodes in the bias generator circuit; and a power switch that receives a power from a power supply and that provides power to the bias generator circuit, the master startup circuit, and the second startup circuit.

Abstract: Power control is facilitated. In accordance with one or more embodiments, power is supplied to power rails of an integrated circuit using a power control circuit including a power regulator and a reset circuit that is responsive to a supply voltage. The power regulator provides power to the power rails, based upon a control signal. The reset circuit controls the power regulator to provide power to the power rails independently of the control signal when the supply voltage is below an operational voltage level, and controls the power regulator to provide power to the power rails in response to the control signal when the supply voltage reaches the operational voltage level.