Patents by Inventor Kevin P. Martin

Kevin P. Martin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7554347
    Abstract: Optoelectronic probe cards, methods of fabrication, and methods of use, are disclosed. Briefly described, one exemplary embodiment includes an optoelectronic probe card adapted to test an electrical quality and an optical quality of an optoelectronic structure under test having electrical and optical components.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: June 30, 2009
    Assignee: Georgia Tech Research Corporation
    Inventors: Tony Mule′, Hiren Thacker, Muhannad Bakir, James D. Meindl, Thomas K. Gaylord, Kevin P. Martin, Paul Kohl
  • Patent number: 7513270
    Abstract: A safety relief valve provides for the equalization of backpressure across a valve spindle by providing for flow of fluid between equal sized upper and lower surfaces of the spindle in order to render the valve set point independent of backpressure, such that opening characteristics are controlled solely by the setting of the valve control spring. A seal preferably formed of TEFLON® is provided to prevent the escape of fluid from the valve body, which would otherwise adversely affect the pressure balance between the upper and lower surfaces.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: April 7, 2009
    Assignee: Flow-Safe, Inc.
    Inventors: Kevin P. Martin, Nelson R. Timm
  • Patent number: 7468558
    Abstract: Devices having one or more of the following: an input/output (I/O) interconnect system, an optical I/O interconnect, an electrical I/O interconnect, a radio frequency I/O interconnect, are disclosed. A representative I/O interconnect system includes a first substrate and a second substrate. The first substrate includes a compliant pillar vertically extending from the first substrate. The compliant pillar is constructed of a first material. The second substrate includes a compliant socket adapted to receive the compliant pillar. The compliant socket is constructed of a second material.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: December 23, 2008
    Assignee: Georgia Tech Research Corporation
    Inventors: Muhannad S. Bakir, Kevin P. Martin, James D. Meindl
  • Patent number: 7431796
    Abstract: An apparatus for low-damage, anisotropic etching of substrates having the substrate mounted upon a mechanical support located within an ac or dc plasma reactor. The mechanical support is independent of the plasma reactor generating apparatus and capable of being electrically biased. The substrate is subjected to a plasma of low-energy electrons and a species reactive with the substrate. An additional structure capable of being electrically biased can be placed within the plasma to control further the extraction or retardation of particles from the plasma.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: October 7, 2008
    Assignee: Georgia Tech Research Corporation
    Inventors: Kevin P. Martin, Harry P. Gillis, Dmitri A. Choutov
  • Patent number: 7099525
    Abstract: Devices and systems having one or more of the following components: a compliant pillar with a modified tip surface (non-flat tip) and a corresponding compliant socket; an optical/electrical I/O interconnect and a corresponding compliant socket; a lens/waveguide optical pillar, a polymer bridge, and an L-shaped pillar, are described herein. In addition, methods of making these components and methods of using these components are disclosed herein.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: August 29, 2006
    Assignee: Georgia Tech Research Corporation
    Inventors: Muhannad S. Bakir, Kevin P. Martin, James D. Meindl
  • Patent number: 6954576
    Abstract: Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: October 11, 2005
    Assignee: Georgia Tech Research Corporation
    Inventors: Tony Mule′, Chirag Patel, James D. Meindl, Thomas K. Gaylord, Elias N. Glytsis, Kevin P. Martin, Stephen M. Schultz, Muhannad Bakir, Hollie Reed, Paul Kohl
  • Patent number: 6852195
    Abstract: An apparatus for low-damage, anisotropic etching of substrates having the substrate mounted upon a mechanical support located within an ac or dc plasma reactor. The mechanical support is independent of the plasma reactor generating apparatus and capable of being electrically biased. The substrate is subjected to plasma of low-energy electrons and a species reactive with the substrate. An additional structure capable of being electrically biased can be placed within the plasma to control further the extraction or retardation of particles from the plasma.
    Type: Grant
    Filed: May 15, 2001
    Date of Patent: February 8, 2005
    Assignee: Georgia Tech Research Corporation
    Inventors: Kevin P. Martin, Harry P. Gillis, Dmitri A. Choutov
  • Publication number: 20040264840
    Abstract: Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.
    Type: Application
    Filed: July 21, 2004
    Publication date: December 30, 2004
    Inventors: Tony Mule, Chirag Patel, James D. Meindl, Thomas K. Gaylord, Elias N. Glytsis, Kevin P. Martin, Stephen M. Schultz, Muhannad Bakir, Hollie Reed, Paul Kohl
  • Publication number: 20040184704
    Abstract: Briefly described, embodiments of this disclosure, among others, include waveguide systems, methods of directing optical energy, input/output (I/O) interconnect systems, methods for fabricating an off-surface and curved optical waveguide, methods of aligning substrates, and methods of separating two microelectronic substrates. One exemplary waveguide system, among others, includes, a first substrate having an off-surface and curved optical waveguide disposed thereon.
    Type: Application
    Filed: October 31, 2003
    Publication date: September 23, 2004
    Inventors: Muhannad S. Bakir, Kevin P. Martin, James D. Meindl
  • Publication number: 20040184703
    Abstract: Devices and systems having one or more of the following components: a compliant pillar with a modified tip surface (non-flat tip) and a corresponding compliant socket; an optical/electrical I/O interconnect and a corresponding compliant socket; a lens/waveguide optical pillar, a polymer bridge, and an L-shaped pillar, are described herein. In addition, methods of making these components and methods of using these components are disclosed herein.
    Type: Application
    Filed: August 25, 2003
    Publication date: September 23, 2004
    Inventors: Muhannad S. Bakir, Kevin P. Martin, James D. Meindl
  • Patent number: 6785458
    Abstract: Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: August 31, 2004
    Assignee: Georgia Tech Research Corporation
    Inventors: Tony Mule′, Chirag Patel, James D. Meindl, Thomas K. Gaylord, Elias N. Glytsis, Kevin P. Martin, Stephen M. Schultz, Muhannad Bakir, Hollie Reed, Paul Kohl
  • Publication number: 20040163763
    Abstract: An apparatus for low-damage, anisotropic etching of substrates having the substrate mounted upon a mechanical support located within an ac or dc plasma reactor. The mechanical support is independent of the plasma reactor generating apparatus and capable of being electrically biased. The substrate is subjected to a plasma of low-energy electrons and a species reactive with the substrate. An additional structure capable of being electrically biased can be placed within the plasma to control further the extraction or retardation of particles from the plasma.
    Type: Application
    Filed: February 23, 2004
    Publication date: August 26, 2004
    Inventors: Kevin P. Martin, Harry P. Gillis, Dimitri A. Choutov
  • Patent number: 6690081
    Abstract: Devices and method of fabrication thereof are disclosed. A representative device includes one or more lead packages. The lead packages include a substrate including a plurality of die pads, an overcoat polymer layer, a plurality of sacrificial polymer layers disposed between the substrate and the overcoat polymer layer, and a plurality of leads. Each lead is disposed upon the overcoat polymer layer having a first portion disposed upon a die pad. The sacrificial polymer layer can be removed to form one or more air-gaps.
    Type: Grant
    Filed: November 19, 2001
    Date of Patent: February 10, 2004
    Assignee: Georgia Tech Research Corporation
    Inventors: Muhannad S. Bakir, Hollie Reed, Paul Kohl, Chirag S. Patel, Kevin P. Martin, James Meindl
  • Publication number: 20040017215
    Abstract: Optoelectronic probe cards, methods of fabrication, and methods of use, are disclosed. Briefly described, one exemplary embodiment includes an optoelectronic probe card adapted to test an electrical quality and an optical quality of an optoelectronic structure under test having electrical and optical components.
    Type: Application
    Filed: March 17, 2003
    Publication date: January 29, 2004
    Inventors: Tony Mule, Hiren Thacker, Muhannad Bakir, James D. Meindl, Thomas K. Gaylord, Kevin P. Martin, Paul Kohn
  • Publication number: 20030206680
    Abstract: Devices having one or more of the following: an input/output (I/O) interconnect system, an optical I/O interconnect, an electrical I/O interconnect, a radio frequency I/O interconnect, are disclosed. A representative I/O interconnect system includes a first substrate and a second substrate. The first substrate includes a compliant pillar vertically extending from the first substrate. The compliant pillar is constructed a first material. The second substrate includes a compliant socket adapted to receive the compliant pillar. The compliant socket is constructed of a second material.
    Type: Application
    Filed: May 5, 2003
    Publication date: November 6, 2003
    Applicant: Georgia Tech Research Corporation
    Inventors: Muhannad S. Bakir, Kevin P. Martin, James D. Meindl
  • Patent number: D541656
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: May 1, 2007
    Inventor: Kevin P. Martin
  • Patent number: D482621
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: November 25, 2003
    Inventor: Kevin P. Martin
  • Patent number: D482622
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: November 25, 2003
    Inventor: Kevin P. Martin
  • Patent number: D482623
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: November 25, 2003
    Inventor: Kevin P. Martin
  • Patent number: D489001
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: April 27, 2004
    Inventor: Kevin P. Martin