Patents by Inventor Kevin P. O'Connor

Kevin P. O'Connor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090083312
    Abstract: A method and a system is provided for composing a document for a selected topic based on a plurality of information sources. The document composition system includes a note gathering module including a first display window for acquiring a plurality of notes from the plurality of associated information sources. A topic writing project database is provided in communication with the note gathering module and is capable of receiving and storing the plurality of notes. A note indexing module is provided in communication with the writing project database and includes a second display window for prioritizing the plurality of notes. The plurality of notes can be indexed into a series of logically related writing categories. A note consolidating module is provided in communication with the writing project database, the note consolidating module including a third display window for consolidating select ones of the plurality of notes to create the document.
    Type: Application
    Filed: September 19, 2008
    Publication date: March 26, 2009
    Inventor: Kevin P. O'Neil
  • Publication number: 20080309324
    Abstract: A magnetic rotational position sensor that employs a single magnet mounted on a rotating turret that rotates on a housing that is fixedly mounted about a fixed ball stud. The turret is arranged to rotate around the ball stud in a first plane. A magnetic field orientation sensor is mounted to the housing, such that the magnet rotates along an arc tangent to the Hall effect sensor. The ball of the ball stud forms one half of a universal joint, the other half being formed by a shaft termination that is mounted to rotate with the turret, and also mounted for rotation in a second plane perpendicular to the first plane of the turret.
    Type: Application
    Filed: June 18, 2007
    Publication date: December 18, 2008
    Applicant: KEY SAFETY SYSTEMS, INC.
    Inventors: Steven R. Stuve, Kevin P. O'Connor
  • Publication number: 20080083168
    Abstract: A drive assembly for a vehicle door is provided. The drive assembly includes a motor having a driving member. The drive assembly further includes a housing having a shaft rotatably received therein. The drive assembly further includes an input member being rotatably received upon the shaft. The input member is operatively associated with the driving member. The drive assembly further includes a rotor fixedly secured to the shaft. The drive assembly further includes first and second Hall effect sensor modules mounted to the housing in a facing spaced relationship with respect to the plurality of teeth of the rotor that generate first and second signals, respectively. The first and second signals have a quadrature relationship with respect to one another and indicate a rotational direction of the rotor when the plurality of teeth are rotating past the first and second Hall effect sensor modules.
    Type: Application
    Filed: May 9, 2007
    Publication date: April 10, 2008
    Inventors: Thomas L. Booth, Kevin P. O'Connor
  • Patent number: 7344972
    Abstract: The invention provides a layer of photosensitive material that may be directly patterned. The photosensitive material may then be decomposed to leave voids or air gaps in the layer. This may provide a low dielectric constant layer with reduced resistance capacitance delay characteristics.
    Type: Grant
    Filed: April 21, 2004
    Date of Patent: March 18, 2008
    Assignee: Intel Corporation
    Inventors: Michael D. Goodner, Kevin P. O'Brien, Grant M. Kloster, Robert P. Meagley
  • Patent number: 7335587
    Abstract: A method for forming a semiconductor device is disclosed wherein atomic layer deposition (ALD) precursor species and/or by-product absorbed by an ILD are outgassed and/or neutralized prior to subsequently patterning the semiconductor device, thereby improving the ability to accurately define subsequently formed interconnect structures in the ILD.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: February 26, 2008
    Assignee: Intel Corporation
    Inventors: Steven W. Johnston, Kevin P. O'Brien, Sridhar Balakrishnan
  • Patent number: 7294568
    Abstract: A method of forming air gaps in the interconnect structure of an integrated circuit device. The air gaps may be formed by depositing sacrificial layer over a dielectric layer and then depositing a permeable hard mask over the sacrificial layer. The sacrificial layer is subsequently removed to form air gaps. The permeable hard mask may have a thickness of less than approximately 250 nm, and internal stresses within the permeable hard mask may be controlled to prevent deformation of this layer. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: November 13, 2007
    Assignee: Intel Corporation
    Inventors: Michael D. Goodner, Kevin P. O'Brien, Grant M. Kloster
  • Patent number: 7289971
    Abstract: Utilization of the E-Metro Community and Personal Information Agents assure an effective and comprehensive agent-rule based command and control of informational assets in a networked computer environment. The concerns of informational privacy and informational self-determination are addressed squarely by the invention affording persons and entities a trusted means to author, secure, search, process, and exchange personal and/or confidential information in a networked computer environment. The formation of trusted electronic communities wherein members command and control their digital persona, exchanging or brokering for value the trusted utility of their informational assets is made possible by the invention. The present invention provides for the trusted utilization of personal data in electronic markets, providing both communities and individuals aggregate and individual rule-based control of the processing of their personal data.
    Type: Grant
    Filed: July 15, 1999
    Date of Patent: October 30, 2007
    Inventors: Kevin P. O'Neil, Glenn R. Seidman
  • Patent number: 7267943
    Abstract: The present invention relates to methods and assays for detecting bacteriophage MS2 in a sample.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: September 11, 2007
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Kevin P. O'Connell, Akbar S. Khan, Cheng J. Cao, Jennifer R. Bucher, Mark V. Gostomski, James J. Valdes, Patricia E. Anderson
  • Patent number: 7264924
    Abstract: The present invention relates to methods and assays for detecting bacteriophage MS2 in a sample.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: September 4, 2007
    Assignee: The United States of America as Represented by the Secretary of the Army
    Inventors: Kevin P. O'Connell, Akbar S. Khan, Cheng J. Cao, Jennifer R. Bucher, Mark V. Gostomski, James J. Valdes, Patricia E. Anderson
  • Patent number: 7251611
    Abstract: An economic supply optimization system is provided whereby an optimal machine dismantling configuration of a machine supply is determined to meet a parts demand at a lowest cost. The parts supply is calculated and it is determined what portions of the demand cannot be met from the machine supply and what portions of the demand it is not economically justifiable to meet from the machine supply. A parts supply is then determined from the machine supply. The remaining parts demand is matched to the parts supply to create a list of parts covered by the parts supply and a list of parts not covered by the parts supply, if there are any. The optimal dismantling configuration of the machine supply is calculated for the covered parts list and an optimal harvesting configuration is calculated for the not-covered parts list.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: July 31, 2007
    Assignee: International Business Machines Corporation
    Inventors: Steve Abbott, William E. Dickey, William F. Holden, Jr., Larry M. Leibovich, Joseph V. Stehle, Ronald A. Warfel, Yung-Joon Lee, Kevin P. O'Connor, Pitipong Veerakamolmal
  • Patent number: 7242180
    Abstract: Two sensor modules that each contain two Hall effect sensors are positioned with respect to each other and with respect to a circuit board in a gear tooth sensor assembly. The sensor modules are arranged rotated in the plane of a positioning surface 120° with respect to each other, and tilted toward each other 15°. Sensor leads are bent at an angle of 98.64° such that the leads on both sensors pass perpendicularly through holes in a single circuit board tilted at an angle of 4.30° away from a plane tangent to the gear at a point halfway between the sensors. The sensor package is formed by a plastic mounting bracket arranged to position the sensor modules with respect to each other and the circuit board. The first two angles are selected, and the second two angles are determined so that the sensors are inserted perpendicular to the circuit board.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: July 10, 2007
    Assignee: Key Safety Systems, Inc.
    Inventor: Kevin P. O'Connor
  • Patent number: 7238604
    Abstract: A thin hard mask is formed over a semiconductor substrate. The thin hard mask allows diffusion of a sacrificial material or pore-forming agent therethrough to form an underlying air gap or porous dielectric region. The thin hard mask may be a polymer or an initially porous material that may be later densified. The thin hard mask may be used to prevent etch steps used in forming an unlanded via from reaching layers below the hard mask.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: July 3, 2007
    Assignee: Intel Corporation
    Inventors: Grant M. Kloster, Kevin P. O'Brien, David H. Gracias, Hyun-Mog Park, Vijayakumar S. Ramachandrarao
  • Patent number: 7235355
    Abstract: The present invention relates to methods and assays for detecting bacteriophage MS2 in a sample.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: June 26, 2007
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Kevin P. O'Connell, Akbar S. Khan, Cheng J. Cao, Jennifer R. Bucher, Mark V. Gostomski, James J. Valdes, Patricia E. Anderson
  • Patent number: 7220540
    Abstract: The present invention relates to methods and assays for detecting bacteriophage MS2 in a sample.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: May 22, 2007
    Assignee: United States of America as represented by the Secretary of the Army
    Inventors: Kevin P. O'Connell, Akbar S. Khan, Cheng J. Cao, Jennifer R. Bucher, Mark V. Gostomski, James J. Valdes, Patricia E. Anderson
  • Patent number: 7126223
    Abstract: A method is disclosed of forming an air gap using etch back of an inter layer dielectric (ILD) with self-alignment to metal pattern. The method entails forming a first metallization layer deposited on a first dielectric, forming a second metallization layer deposited on a second dielectric, wherein the second metallization layer is spaced apart from the first metallization layer, forming a sacrificial ILD between the first and second metallization layers, forming a diffusion layer over the first and second metallization layers and over the sacrificial ILD, and removing the sacrificial ILD to form an air gap between the first and second metallization layers. This method is particular applicable for dual copper damascene processes.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: October 24, 2006
    Assignee: Intel Corporation
    Inventors: James Powers, Kevin P. O'Brien
  • Patent number: 7119019
    Abstract: Capping of copper structures in hydrophobic interlayer dielectric layer, using aqueous electro-less bath is described herein.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: October 10, 2006
    Assignee: Intel Corporation
    Inventors: Kevin P. O'Brien, Justin K. Brask
  • Patent number: 7109557
    Abstract: A method of forming a microelectronic structure and its associated structures is described. In one embodiment, a substrate is provided with a sacrificial layer disposed on a hard mask layer, and a metal layer disposed in a trench of the substrate and on the sacrificial layer. The metal layer is then removed at a first removal rate wherein a dishing is induced on a top surface of the metal layer until the sacrificial layer is exposed, and simultaneously removing the metal layer and the sacrificial layer at a second removal rate without substantially removing the hard mask.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: September 19, 2006
    Assignee: Intel Corporation
    Inventors: Chris E. Barns, Kevin P. O'Brien, Anne E. Miller
  • Patent number: 7101798
    Abstract: Several techniques are described for modulating the etch rate of a sacrificial light absorbing material (SLAM) by altering its composition so that it matches the etch rate of a surrounding dielectric. This is particularly useful in a dual damascene process where the SLAM fills a via opening and is etched along with a surrounding dielectric material to form trenches overlying the via opening.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: September 5, 2006
    Assignee: Intel Corporation
    Inventors: Michael D. Goodner, Robert P. Meagley, Kevin P. O'Brien
  • Patent number: 7071126
    Abstract: An interlayer dielectric may be exposed to a gas cluster ion beam to densify an upper layer of the interlayer dielectric. As a result, the upper layer of the interlayer dielectric may be densified without separate deposition steps and without the need for etch stops that may adversely affect the capacitance of the overall structure.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: July 4, 2006
    Assignee: Intel Corporation
    Inventors: Steven W. Johnston, Kevin P. O'Brien
  • Patent number: 7034399
    Abstract: A dielectric layer is made porous by treating the dielectric material after metal interconnects are formed in or through that layer. The porosity lowers the dielectric constant of the dielectric material. The dielectric material may be subjected to an electron beam or a sonication bath to create the pores. The structure has smooth sidewalls for metal interconnects extending through the dielectric layer.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: April 25, 2006
    Assignee: Intel Corporation
    Inventors: Grant M. Kloster, Kevin P. O'Brien, Justin K. Brask, Michael D. Goodner, Donald Bruner