Patents by Inventor Kevin P. O'Connor

Kevin P. O'Connor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180301619
    Abstract: An embodiment includes an apparatus comprising: a substrate; and a perpendicular magnetic tunnel junction (pMTJ) comprising a fixed layer and first and second free layers; wherein (a) the first free layer includes Cobalt (Co), Iron (Fe), and Boron (B), and (b) the second free layer is epitaxial and includes Manganese (Mn) and Gallium (Ga). Other embodiments are described herein.
    Type: Application
    Filed: June 26, 2015
    Publication date: October 18, 2018
    Inventors: Kaan Oguz, Kevin P. O'Brien, Brian S. Doyle, David L. Kencke, Charles C. Kuo, Robert S. Chau
  • Publication number: 20180287050
    Abstract: MTJ material stacks with a laterally strained free magnetic layer, STTM devices employing such stacks, and computing platforms employing such STTM devices. In some embodiments, perpendicular pMTJ material stacks included free magnetic layers that are compressively strained laterally by a surrounding material, which increases coercive field strength for a more stable device. In some embodiments, a pMTJ material stack is encased in a compressive-stressed material. In some further embodiments, a pMTJ material stack is encased first in a dielectric shell, permitting a conductive material to be deposited over the shell as the compressive-stressed, strain-inducing material layer.
    Type: Application
    Filed: September 25, 2015
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Prashanth P. Madras, MD Tofizur Rahman, Christopher J. Wiegand, Brian Maertz, Oleg Golonzka, Kevin P. O'Brien, Mark L. Doczy, Brian S. Doyle, Tahir Ghani, Kaan Oguz
  • Publication number: 20180248116
    Abstract: Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for removing a re-deposited layer and/or interrupting the electrical continuity of a re-deposited layer that may form on one or more sidewalls of an STTM element during its formation. Devices and systems including such STTM elements are also described.
    Type: Application
    Filed: September 18, 2015
    Publication date: August 30, 2018
    Applicant: Intel Corporation
    Inventors: Mark L. DOCZY, Brian S. DOYLE, Charles C. KUO, Kaan OGUZ, Kevin P. O'BRIEN, Satyarth SURI, Tejaswi K. INDUKURI
  • Publication number: 20180248115
    Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include one or more electrode interface material layers disposed between a an electrode metal, such as TiN, and a seed layer of an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. The electrode interface material layers may include either or both of a Ta material layer or CoFeB material layer. In some Ta embodiments, a Ru material layer may be deposited on a TiN electrode surface, followed by the Ta material layer. In some CoFeB embodiments, a CoFeB material layer may be deposited directly on a TiN electrode surface, or a Ta material layer may be deposited on the TiN electrode surface, followed by the CoFeB material layer.
    Type: Application
    Filed: September 25, 2015
    Publication date: August 30, 2018
    Applicant: Intel Corporation
    Inventors: Kaan Oguz, Kevin P. O'Brien, Christopher J. Wiegand, MD Tofizur Rahman, Brian S. Doyle, Mark L. Doczy, Oleg Golonzka, Tahir Ghani, Justin S. Brockman
  • Publication number: 20180248114
    Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such STTM devices. In some embodiments, perpendicular MTJ material stacks with free magnetic layers are magnetically coupled through a metal material layer for improved stability and low damping. In some advantageous embodiments, layers of a free magnetic material stack are magnetically coupled through a coupling layer of a metal comprising at least molybdenum (Mo). The Mo may be in pure form or alloyed with other constituents.
    Type: Application
    Filed: September 25, 2015
    Publication date: August 30, 2018
    Applicant: Intel Corporation
    Inventors: Kaan Oguz, Kevin P. O'Brien, Christopher J. Wiegand, MD Tofizur Rahman, Brian S. Doyle, Mark L. Doczy, Oleg Golonzka, Tahir Ghani, Justin S. Brockman
  • Publication number: 20180240969
    Abstract: Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for interrupting the electrical continuity of a re-deposited layer that may form on one or more sidewalls of an STTM element during its formation. Devices and systems including such STTM elements are also described.
    Type: Application
    Filed: September 18, 2015
    Publication date: August 23, 2018
    Applicant: INTEL CORPORATION
    Inventors: MARK L. DOCZY, BRIAN S. DOYLE, CHARLES C. KUO, KAAN OGUZ, KEVIN P. O'BRIEN, SATYARTH SURI, TEJASWI K. INDUKURI
  • Publication number: 20180240970
    Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include a multi-layered filter stack disposed between a fixed magnetic layer and an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. In some embodiments, non-magnetic layers of the filter stack include at least one of Ta, Mo, Nb, W, or Hf. These transition metals may be in pure form or alloyed with other constituents.
    Type: Application
    Filed: September 25, 2015
    Publication date: August 23, 2018
    Applicant: Intel Corporation
    Inventors: Kaan Oguz, Kevin P. O'Brien, Christopher J. Wiegand, MD Tofizur Rahman, Brian S. Doyle, Mark L. Doczy, Oleg Golonzka, Tahir Ghani, Justin S. Brockman
  • Patent number: 10008557
    Abstract: Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: June 26, 2018
    Assignee: Intel Corporation
    Inventors: Christopher J. Jezewski, Kevin P. O'Brien
  • Publication number: 20180165065
    Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) device with out-of-plane magnetizations for its free and fixed magnetic layers, and configured to have a magnetization offset away from a center and closer to a switching threshold of the MTJ device; and logic for generating random numbers according to a resistive state of the MTJ device.
    Type: Application
    Filed: June 17, 2015
    Publication date: June 14, 2018
    Inventors: Charles C. KUO, Justin S. BROCKMAN, Juan G. ALZATE VINASCO, Kaan OGUZ, Kevin P. O'BRIEN, Brian S. DOYLE, Mark L. DOCZY, Satyarth SURI, Robert S. CHAU, Prashant MAJHI, Ravi PILLARISETTY, Elijah V. KARPOV
  • Patent number: 9962446
    Abstract: A solid dispersion comprising at least one active ingredient in at least one hydroxyalkyl methylcellulose having a DS of from 1.0 to 2.7 and an MS of from 0.40 to 1.30, wherein DS is the degree of substitution of methoxyl groups and MS is the molar substitution of hydroxyalkoxyl groups, can be produced by extrusion or spray-drying.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: May 8, 2018
    Assignee: Dow Global Technologies LLC
    Inventors: Nicholas S. Grasman, Steven J. Guillaudeu, Mark J. Hall, Uma Shrestha, Maureen L. Rose, William W. Porter, III, Wesley J. Spaulding, Kevin P. O'donnell, True L. Rogers
  • Publication number: 20170271578
    Abstract: A method including forming a device stack including a dielectric layer between a fixed magnetic layer and a free magnetic layer on a fully-crystalline sacrificial film or substrate including a crystal lattice similar to the crystal lattice of the dielectric material; and transferring the device stack from the sacrificial film to a device substrate. An apparatus including a device stack including a dielectric layer between a fixed magnetic layer and a free magnetic layer on a device substrate wherein the fixed magnetic layer and the free magnetic layer each have a crystalline lattice conforming to a crystalline lattice of the sacrificial film or substrate on which they were formed prior to transfer to the device substrate.
    Type: Application
    Filed: September 26, 2014
    Publication date: September 21, 2017
    Inventors: Kevin P. O'BRIEN, Brian S. DOYLE, Kaan OGUZ, Robert S. CHAU, Satyarth SURI
  • Publication number: 20170271576
    Abstract: A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.
    Type: Application
    Filed: September 26, 2014
    Publication date: September 21, 2017
    Inventors: Kevin P. O'BRIEN, Kaan OGUZ, Brian S. DOYLE, Mark L. DOCZY, Charles C. KUO, Robert S. CHAU
  • Publication number: 20170119692
    Abstract: A drug-containing microcapillary film having: (a) a matrix comprising a polymer having a glass transition temperature less than 190° C.; wherein the matrix has a thickness from 5 to 2000 microns; (b) channels disposed in parallel in the matrix, wherein the channels are separated from each other by at least 1 micron, and wherein total cross-sectional area of the channels is from 5 to 70% of total cross-sectional area of the film; and (c) at least one drug disposed in the matrix and/or in the channels.
    Type: Application
    Filed: June 5, 2015
    Publication date: May 4, 2017
    Inventors: Nicholas S. GRASMAN, Kevin P. O'DONNELL, True L. ROGERS
  • Publication number: 20170053977
    Abstract: Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.
    Type: Application
    Filed: November 3, 2016
    Publication date: February 23, 2017
    Inventors: Christopher J. Jezewski, Kevin P. O'Brien
  • Patent number: 9490313
    Abstract: Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: November 8, 2016
    Assignee: Intel Corporation
    Inventors: Christopher J. Jezewski, Kevin P. O'Brien
  • Publication number: 20150340424
    Abstract: Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.
    Type: Application
    Filed: July 31, 2015
    Publication date: November 26, 2015
    Inventors: Christopher J. Jezewski, Kevin P. O'Brien
  • Patent number: 9129817
    Abstract: Semiconductor packages including magnetic core inductor (MCI) structures for integrated voltage regulators are described. In an example, a semiconductor package includes a package substrate and a semiconductor die coupled to a first surface of the package substrate. The semiconductor die has a first plurality of metal-insulator-metal (MIM) capacitor layers thereon. The semiconductor package also includes a magnetic core inductor (MCI) die coupled to a second surface of the package substrate. The MCI die includes one or more slotted inductors and has a second plurality of MIM capacitor layers thereon.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 8, 2015
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Kevin P. O'Brien, Henning Braunisch, Krishna Bharath
  • Patent number: 9129844
    Abstract: Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: September 8, 2015
    Assignee: Intel Corporation
    Inventors: Christopher J. Jezewski, Kevin P. O'Brien
  • Publication number: 20150191374
    Abstract: Methods and compositions for removing a targeted constituent from water are disclosed. The water including the targeted constituent may be transported into a reactor and the reactor may include a magnet and zero valent iron particles. The targeted constituent can chemically react with the zero valent iron particles and the particles may then be attracted to the magnet. The water may then pass out of the reactor free of the targeted constituent. Additionally, the zero valent iron particles may be regenerated and reused.
    Type: Application
    Filed: July 29, 2014
    Publication date: July 9, 2015
    Applicant: ECOLAB USA INC.
    Inventors: Daniel E. Schwarz, Adam A. Smith, Gordon M. Carter, Kevin P. O'Leary
  • Publication number: 20150140091
    Abstract: A solid dispersion comprising at least one active ingredient in at least one hydroxyalkyl methylcellulose having a DS of from 1.0 to 2.7 and an MS of from 0.40 to 1.30, wherein DS is the degree of substitution of methoxyl groups and MS is the molar substitution of hydroxyalkoxyl groups, can be produced by extrusion or spray-drying.
    Type: Application
    Filed: July 12, 2013
    Publication date: May 21, 2015
    Applicant: Dow Global Technologies LLC
    Inventors: Nicholas S. Grasman, Steven J. Guillaudeu, Mark J. Hall, Uma Shrestha, Maureen L. Rose, William W. Porter, III, Wesley J. Spaulding, Kevin P. O'donnell, True L. Rogers